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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M16C/1N датащи(PDF) 67 Page - Renesas Technology Corp |
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M16C/1N датащи(HTML) 67 Page - Renesas Technology Corp |
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67 / 238 page  Rev.1.00 Oct 20, 2004 page 55 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z Instruction Interrupt sequence Instruction in interrupt routine Time Interrupt response time (a) (b) Interrupt request acknowledged Interrupt request generated (a) A time from when an interrupt request is generated till when the instruction then executing is completed. The length of this time varies with the instruction being executed. The DIVX instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register). (b) A time during which the interrupt sequence is executed. For details, see the table below. Note, however, that the values in this table must be increased 2 cycles for the DBC interrupt and 1 cycle for the address match and single-step interrupts. Locate an interrupt vector address in an even address, if possible. Interrupt vector address Without wait Even Even Odd Odd Even Odd Even Odd 18 cycles 19 cycles 19 cycles 20 cycles Stack pointer (SP) value 10.1.5.6 Interrupt Response Time 'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 10.5 shows the interrupt response time. Figure 10.5 Interrupt response time |
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