M16CSLASH1N datasheet(69/238 Pages) RENESAS

69 / 238 page

Rev.1.00

Oct 20, 2004

page 57 of 222

M16C/1N Group

10. Interrupt

REJ09B0007-0100Z

(2) Stack pointer (SP) contains odd number

[SP]

(Odd)

[SP] - 1 (Even)

[SP] - 2 (Odd)

[SP] - 3 (Even)

[SP] - 4 (Odd)

[SP] - 5 (Even)

Address

Sequence in which order

registers are saved

(2)

(1)

Finished saving registers

in four operations.

(3)

(4)

(1) Stack pointer (SP) contains even number

[SP]

(Even)

[SP] - 1 (Odd)

[SP] - 2 (Even)

[SP] - 3 (Odd)

[SP] - 4 (Even)

[SP] - 5 (Odd)

Address

Program counter (PCM)

Stack area

Flag register (FLGL)

Program counter (PCL)

Sequence in which order

registers are saved

Finished saving registers

in two operations.

Program counter (PCM)

Stack area

Flag register (FLG

Program counter (PCL)

Saved simultaneously,

all 8 bits

Flag register

(FLGH)

Program

counter (PCH)

Flag register

(FLGH)

Program

counter (PCH)

(2) Saved simultaneously,

all 16 bits

(1) Saved simultaneously,

all 16 bits

Note 1: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is

acknowledged. After registers are saved, the SP content is [SP] minus 4.

The operation of saving registers carried out in the interrupt sequence is dependent on whether the

content of the stack pointer (Note 1), at the time of acceptance of an interrupt request, is even or

odd. If the content of the stack pointer (Note 1) is even, the content of the flag register (FLG) and

the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are

saved in two steps, 8 bits at a time. Figure 10.7 shows the operation of the saving registers.

Note 1: This is the stack pointer indicated by the U flag.

Figure 10.7 Operation of saving registers

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