M16CSLASH1N datasheet(80/238 Pages) RENESAS

80 / 238 page

Rev.1.00

Oct 20, 2004

page 68 of 222

M16C/1N Group

11. Watchdog Timer

REJ09B0007-0100Z

Write to the watchdog timer

start register

(address 000E16)

RESET

Watchdog timer

interrupt request

Note 1: This bit is set to "1" once, can not be clear to "0" by software.

Reset (Note 1)

"PM12=1"

"PM12=0"

Watchdog timer

Set to

"7FFF16"

1/128

1/16

"CM07 = 0"

"WDC7 = 1"

"CM07 = 0"

"WDC7 = 0"

"CM07 = 1"

BCLK

1/2

Prescaler

11. Watchdog Timer

The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom-

mend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter

which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt

or reset is generated when an underflow occurs in the watchdog timer. A watchdog timer interrupt or reset

is selected by bit 2 of the processor mode register 1. When XIN is selected for the BCLK, bit 7 of the

watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128).

When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog

timer control register (address 000F16).

When XIN is selected in BCLK

Watchdog timer cycle =

When XCIN is selected in BCLK

Watchdog timer cycle =

For example, when BCLK is 10MHz and the prescaler division ratio is set to 16, the watchdog timer cycle is

approximately 52.4 ms.

The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when

a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is

reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by

writing to the watchdog timer start register (address 000E16).

Figure 11.1 shows the block diagram of the watchdog timer. Figure 11.2 shows the watchdog timer-related

registers.

Prescaler division ratio (16 or 128) x watchdog timer count (32768)

BCLK

Prescaler division ratio (2) x watchdog timer count (32768)

BCLK

Figure 11.1 Block diagram of watchdog timer

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