M16CSLASH1N datasheet(70/238 Pages) RENESAS

70 / 238 page

Rev.1.00

Oct 20, 2004

page 58 of 222

M16C/1N Group

10. Interrupt

REJ09B0007-0100Z

Figure 10.8 Hardware interrupts priorities

10.1.5.9 Returning from an Interrupt Routine

Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag

program counter (PC), both of which have been saved in the stack area. Then control returns to the

program that was being executed before the acceptance of the interrupt request, so that the sus-

pended process resumes.

Return the other registers saved by software within the interrupt routine using the POPM or similar

instruction before executing the REIT instruction.

10.1.5.10 Interrupt Priority

If there are two or more interrupt requests occurring at a point in time within a single sampling

(checking whether interrupt requests are made), the interrupt assigned a higher priority is ac-

cepted.

Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt

priority level select bit. If the same interrupt priority level is assigned, however, the interrupt as-

signed a higher hardware priority is accepted.

Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest

priority), watchdog timer interrupt, etc. are regulated by hardware.

Figure 10.8 shows the priorities of hardware interrupts.

Software interrupts are not affected by the interrupt priority. If an instruction is executed, control

branches invariably to the interrupt routine.

10.1.5.11 Interrupt Priority Level Judge Circuit

This circuit selects the interrupt with the highest priority level when two or more interrupts are

generated simultaneously.

Figure 10.9 shows the interrupt resolution circuit.

Reset

UART0 reception

DBC

Watchdog timer/Oscillation stop detection

Peripheral function

Single step

Address match

High

Low

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