M16CSLASH1N datasheet(37/238 Pages) RENESAS

37 / 238 page

Rev.1.00

Oct 20, 2004

page 25 of 222

M16C/1N Group

6. Clock Generation Circuit

REJ09B0007-0100Z

Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register.

Note 2: fc32 is not included. Do not set to "1" when using low-speed, low power dissipation or on-chip oscillator mode.

Note 3: Changes to "1" when shifting to stop mode.

Note 4: This bit is used to stop the main clock when placing the device in a low-power mode. If you want to operate with XIN after

exiting from the stop mode, set this bit to "0". When operating with a self-excited oscillator, set the system clock select bit

(CM07) to "1" before setting this bit to "1".

Note 5: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.

Note 6: If this bit is set to "1", XOUT turns "H". The built-in feedback resistor remains being ON, so XIN turns pulled up to XOUT ("H")

via the feedback resistor.

Note 7: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from

low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.

Note 8: Set port Xc select bit (CM04) to "1" before setting this bit to "1". Can not write to both bits at the same time.

Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register.

Note 2: The mode of power control cannot be shifted on the stop mode directly from the on-chip oscillator.

If this bit is set to "1", XOUT turns "H", and the built-in feedback resistor is ineffective.

Note 3: This bit can be set to "1" only when both the main clock switch bit (CM22) and clock monitor bit (CM23) are set to "0".

Moreover, this bit is automatically set to "0" if the main clock switch bit (CM22) is set to "1".

Note 4: This bit changes to "1" when shifting from high-speed/middle-speed mode to stop mode or at reset. When shifting from low-

speed/low power dissipation mode to stop mode, the value before stop mode is retained.

Note 5: Can be selected when bit 6 of the system clock control register 0 (address 000616) is "0". If "1", division mode is fixed at 8.

b5 b4

CM07

CM05

CM04

CM03

CM02

CM06

Reserved bit

WAIT peripheral function

clock stop bit

XCIN-XCOUT drive capacity

select bit (Note 3)

Port XC select bit

System clock select bit

(Note 8)

Main clock division select

bit 0 (Note 7)

Main clock (XIN-XOUT)

stop bit (Note 4,5,6)

0 : Do not stop peripheral function clock in wait mode

1 : Stop peripheral function clock in wait mode (Note 2)

0 : LOW

1 : HIGH

All clock stop control bit

(Note 2)

0 : Clock on

1 : All clocks off (stop mode)

0 : I/O port

1 : XCIN-XCOUT generation

0 : On

1 : Off

0 : CM16 and CM17 valid

1 : Division by 8 mode

Set to

"0"

Reserved bit

Set to

"0"

0 : XIN, XOUT

1 : XCIN, XCOUT

CM10

On-chip oscillation stop bit 0 : Oscillation enabled

1 : Oscillation stopped (Note 3)

CM14

XIN-XOUT drive capacity

select bit (Note 4)

0 : LOW

1 : HIGH

CM15

Main clock division

select bit 1 (Note 5)

CM16

CM17

System clock control register 0 (Note 1)

Symbol

CM0

Address

000616

When reset

010010002

Function

Bit name

Bit symbol

System clock control register 1 (Note 1)

Symbol

CM1

Address

000716

When reset

001000002

Function

Bit name

Bit symbol

0 0 : No division mode

0 1 : Division by 2 mode

1 0 : Division by 4 mode

1 1 : Division by 16 mode

b7 b6

Figure 6.2 System clock control registers 0 and 1

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