M16CSLASH1N datasheet(19/238 Pages) RENESAS

19 / 238 page

Rev.1.00

Oct 20, 2004

page 7 of 222

M16C/1N Group

2. Central Processing Unit (CPU)

REJ09B0007-0100Z

2.1 Data Registers (R0, R1, R2, and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to

R3 are the same as R0.

The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.

R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit

data register (R2R0). R3R1 is the same as R2R0.

2.2 Address Registers (A0 and A1)

The A0 register consists of 16 bits, and is used for address register indirect addressing and address

same as A0.

In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).

Figure 2.1 CPU Registers

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB

comprise a register bank. There are two register banks.

USP

ISP

b15

Static base register

User stack pointer

Interrupt stack pointer

b19

INTBL

INTBH

The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.

Interrupt table register

b19

Program counter

R0H (R0's high bits) R0L (R0's low bits)

R1H (R1's high bits) R1L (R1's low bits)

b31

b15

b8 b7

Data registers (Note 1)

Address registers (Note 1)

Frame base registers (Note 1)

Note 1: These registers comprise a register bank. There are two register banks.

b15

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

Reserved area

b15

FLG

Flag register

IPL

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