M16CSLASH1N datasheet(42/238 Pages) RENESAS

42 / 238 page

Rev.1.00

Oct 20, 2004

page 30 of 222

M16C/1N Group

6. Clock Generation Circuit

REJ09B0007-0100Z

6.4 CPU Clock and Peripheral Function Clock

6.4.1 BCLK

The BCLK is the clock that drives the CPU. The clock source for BCLK is as follows: (1) the clock

derived by dividing the main clock by 1, 2, 4, 8, or 16, (2) fc, or (3) the clock derived by dividing the

clock supplied by the on-chip oscillator circuit (fRING) by 1, 2, 4, 8 or 16. After reset, the BCLK is

derived by dividing the fRING by 8.

The main clock division select bit 0 (bit 6 at address 000616) changes to "1" when shifting from high-

speed/medium-speed mode to stop mode and at reset. When shifting from low-speed/low power dis-

sipation mode to stop mode, the value before stop mode is retained.

6.4.2 Peripheral Function Clock

6.4.2.1 f1, f8, f32

The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The

peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral

function clock stop bit (bit 2 at address 000616) to "1" and then executing a WAIT instruction.

6.4.2.2 fAD

This clock has the same frequency as the main clock and is used in A/D conversion.

6.4.2.3 fCAN0

This clock is derived by dividing the main clock by 1, 2, 4, 8, 16 by setting the CAN0 clock select

It is used for the corresponding CAN module.

This clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock

stop bit (bit 2 at address 000616) to "1" and then executing a WAIT instruction.

6.4.2.4 fC32

This clock is derived by dividing the sub-clock by 32. It is used for the timer 1, timer X, timer Y and

timer X counts.

6.4.2.5 fC

This clock has the same frequency as the sub-clock. It is used for BCLK and for the watchdog

timer.

6.4.3 fRING

This clock is supplied by the on-chip oscillator circuit. In the on-chip oscillator mode, the clock divided

by the division ratio selected with the main clock division select bit 0 and bit 1 (bit 6 at address 000616,

and bit 6 and bit 7 at address 000716) is supplied as BCLK. Immediately after reset, 8 divisions of this

clock is supplied as BCLK. The on-chip oscillator oscillation can be set to BCLK when oscillation stop

is detected or with the main clock switching bit (bit 2 at address 000C16).

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