M16CSLASH1N datasheet(64/238 Pages) RENESAS

64 / 238 page

Rev.1.00

Oct 20, 2004

page 52 of 222

M16C/1N Group

10. Interrupt

REJ09B0007-0100Z

Interrupt priority

level select bit

Interrupt priority

level

Priority

order

Level 0

(interrupt disabled)

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

Low

High

b2 b1 b0

Enabled interrupt priority levels

Interrupt levels 1 and above are enabled

Interrupt levels 2 and above are enabled

Interrupt levels 3 and above are enabled

Interrupt levels 4 and above are enabled

Interrupt levels 5 and above are enabled

Interrupt levels 6 and above are enabled

Interrupt levels 7 and above are enabled

All maskable interrupts are disabled

IPL2 IPL1IPL0

IPL

000

001

010

100

101

111

000

001

010

01 1

100

101

11 0

111

10.1.5.1 Interrupt Enable Flag (I flag)

The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting

this flag to "1" enables all maskable interrupts; setting it to "0" disables all maskable interrupts.

This flag is set to "0" after reset.

10.1.5.2 Interrupt Request Bit

The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt

is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hard-

ware. The interrupt request bit can also be set to "0" by software (Do not set this bit to "1").

10.1.5.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)

Set the interrupt priority level using the interrupt priority level select bit, which is one of the compo-

nent bits of the interrupt control register. When an interrupt request occurs, the interrupt priority

level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt

is higher than the IPL. Therefore, setting the interrupt priority level to "0" disables the interrupt.

Table 10.3 lists the settings of interrupt priority levels and Table 10.4 lists the interrupt levels en-

abled, according to the consist of the IPL.

The following are conditions under which an interrupt is accepted:

· interrupt enable flag (I flag) = 1

· interrupt request bit = 1

· interrupt priority level > IPL

The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL

are independent, and they are not affected by one another.

Table 10.3 Settings of interrupt priority levels

Table 10.4 Interrupt levels enabled according

to the contents of the IPL

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