TMP93CS44 datasheet(158/224 Pages) TOSHIBA

158 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-156

Figure 3.10.10 Stop Condition Generation

The bus condition can be indicated by reading the contents of <BB>. <BB> is set to 1

when the start condition on a bus is detected, and is set to 0 when the stop condition is

detected.

(8) Cancel interrupt service request

When the TMP93CS44/S45 is the master mode and transferring a number of clocks

set by the SBICR1<BC2:0> and the SBICR1<ACK> is complete, a serial bus interface

interrupt request (INTS2) is generated.

In the slave mode, the INTS2 is generated when the received slave address is the

same as the value set to the I2CAR and an acknowledge signal is output, when a

GENERAL CALL is received and an acknowledge signal is output, or when

transferring/receiving data is complete after the received slave address is the same as

the value set to the I2CAR and a GENERAL CALL is received.

When the serial bus interface interrupt request occurs, the SBISR<PIN> is cleared

to 0. During the time that the PIN is 0, the SCL pin is set to low level.

Either writing or reading data to or from the SBIDBR sets the <PIN> to 1.

The time from the <PIN> being set to 1 until the SCL pin is released takes tLOW.

Although the <PIN> can be set to 1 by the program, the <PIN> is not cleared to 0

when it is written 0.

(9) Serial bus interface operation mode selection

SBICR2<SBIM1:0> is used to specify the serial bus interface operation mode. Set

<SBIM1:0> to 10 when used in the I2C bus mode after confirming that input signal via

port is high level.

Switch a mode to port after making sure that a bus is free.

(10) Noise detection monitor

The I2C bus is easy to be affected by noise, because the bus is driven by the open

drain and the pull-up resistor.

With the TMP93CS44/S45, the SDA pin output and the SDA line level are compared

at a rise of the SCL line on the bus, and whether data are output correctly on the bus is

detected only in the master transmitter mode.

When the SDA pin output differs from the SDA line level, the SBISR<AL> is set to 1.

When the AL is set to 1, the SDA pin is released and the MST and the TRX are

cleared to 0 by the hardware. The TMP93CS44/S45 changes to the slave receiver mode,

and continues outputting clocks unit transferring data when the AL was set to 1 is

completed.

Either writing or reading data to or from the SBIDBR, or writing data to the SBICR2

clears to the AL to 0.

SCL line

SDA line

Stop condition

TMP93CS44 датащи(PDF) 158 Page - Toshiba Semiconductor

TMP93CS44 датащи(HTML) 158 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL