TMP93CS44 datasheet(10/224 Pages) TOSHIBA

10 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-8

Operation

This section describes the functions and basic operational blocks of TMP93CS44/S45 devices.

See the 7. “Points of Note and Restriction” for the using notice and restrictions for each block.

3.1

CPU

TMP93CS44/S45 devices have a built-in high-performance 16-bit CPU (900/L CPU). (For

CPU operation, see TLCS-900/L CPU in the previous section.)

This section describes CPU functions unique to the TMP93CS44/S45 that are not described in

the previous section.

3.1.1

Reset

When resetting the TMP93CS44/S45 microcontroller, ensure that the power supply

voltage is within the operating voltage range, and that the internal high-frequency

oscillator has stabilized. Then set the RESET input to low level at least for 10 system

clocks (16

µs at 20 MHz). Thus, when turn on the switch, be set to the power supply voltage

is within the operating voltage range, and that the internal high-frequency oscillator has

stabilized. Then hold the RESET input to low level at least for 10 system clocks.

Clock gear is initialized 1/16 mode by reset operation. It means that the system clock

mode fSYS is set to fc/32 (= fc/16 × 1/2).

When reset is accepted, the CPU sets as follows:

•

Program counter (PC) according to reset vector that is stored FFFF00H to FFFF02H.

PC<7:0>

← Stored data in location FFFF00H

PC<15:8>

← Stored data in location FFFF01H

PC<23:16>

← Stored data in location FFFF02H

•

Stack pointer (XSP) for system mode to 100H.

•

Bits IFF2 to IFF0 of status register to 111. (Sets mask register to interrupt level 7.)

•

MAX bit of status register to 1. (Sets to maximum mode.)

•

Bits RFP2 to RFP0 of status register to 000. (Sets register banks to 0.)

When reset is released, instruction execution starts from PC (Reset vector). CPU internal

registers other than the above are not changed.

When reset is accepted, processing for built-in I/Os, ports, and other pins is as follows.

•

Initializes built-in I/O registers as per specifications.

•

Sets port pins (including pins also used as built-in I/Os) to general-purpose

input/output port mode.

•

Pulls up the CLK pin to “H” level.

•

Sets the ALE pin to “L” level (the case of TMP93CS45), to High-impedance (High-Z)

(the case of TMP93CS44).

Note 1: By resetting, register in the CPU except program counter (PC), status register (SR) and

stack pointer (XSP) and the data in internal RAM are not changed.

Note 2: The CLK pin is pulled up to “H” level during reset. When the voltage is put down

externally, there is possible to cause malfunctions.

Figure 3.1.1 and Figure 3.1.2 show the reset timing chart of TMP93CS44 and

TMP93CS45.

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