TMP93CS44 datasheet(18/224 Pages) TOSHIBA

18 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-16

System Clock Control Register 0

Bit symbol

XEN

XTEN

RXEN

RXTEN

RSYSCK

WUEF

PRCK1

PRCK0

SYSCR0

(006EH)

Read/Write

R/W

After reset

Function

High-

frequency

oscillator

(fc)

0: Stop

1: Oscillation

Low-

frequency

oscillator

(fs)

0: Stop

1: Oscillation

High-

frequency

oscillator

(fc) after

released

STOP mode

0: Stop

1: Oscillation

Low-

frequency

oscillator

(fs) after

released

STOP mode

0: Stop

1: Oscillation

Select clock

after

released

STOP mode

0: fc

1: fs

Warm-up

timer

(Write)

0: Don’t care

1: Start timer

(Read)

0: End

warm up

1: Not end

warm up

Select prescaler clock

00: fFPH

01: fs

10: fc/16

11: (Reserved)

System Clock Control Register 1

Bit symbol

SYSCK

GEAR2

GEAR1

GEAR0

SYSCR1

(006FH)

Read/Write

R/W

After reset

Function

Select

system

clock

0: fc

1: fs

Select gear value of high frequency (fc)

000: fc

001: fc/2

010: fc/4

011: fc/8

100: fc/16

101: (Reserved)

110: (Reserved)

111: (Reserved)

Clock Output Control Register

Bit symbol

−

ALEEN

CLKEN

CKOCR

(006DH)

Read/Write

R/W

After reset

0/1 (Note 2)

Function

Always write to “0”.

ALE pin

output control

0: High-Z

output

1: ALE output

CLK pin

output control

0: High-Z

output

1: CLK output

Watchdog Timer Mode Control Register

Bit symbol

WDTE

WDTP1

WDTP0

WARM

HALTM1

HALTM0

RESCR

DRVE

WDMOD

(005CH)

Read/Write

R/W

After reset

Function

WDT control

0: Disable

1: Enable

WDT detection time

00: 2

15/fSYS

01: 2

17/fSYS

10: 2

19/fSYS

11: 2

21/fSYS

Warm-up

timer

0: 2

14/

frequency

inputted

1: 2

16/

frequency

inputted

HALT mode

00: RUN mode

01: STOP mode

10: IDLE1 mode

11: IDLE2 mode

0: Don’t care

1: Connects

WDT

output to

RESET

internally.

Pin state

control in

STOP mode

0: I/O off

1: Remains

the state

before

halt

Note 1: SYSCR1<bit7:4> and CKOCR<bit5:2> are read as “1”.

Note 2: In the TMP93CS44, resetting sets <ALEEN>, <CLKEN> bit to “0” (High-impedance ALE and CLK). In the

TMP93CS45, resetting sets <ALEEN>, <CLKEN> bit to “1” (output ALE and CLK). The CLK pin is internally

pulled up during reset regardless of the product types.

Note 3: Writing “0” to SYSCR1<SYSCK> enables the high-frequency oscillator regardless of the value of

SYSCR0<XEN>. Additionally, writing “1” to <SYSCK> register enebles the low-frequency oscillator

regardless of th value of SYSCR0<XTEN>.

Figure 3.3.3 I/O Registers about Dual Clock, Standby

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