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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP93CS44 датащи(PDF) 97 Page - Toshiba Semiconductor |
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TMP93CS44 датащи(HTML) 97 Page - Toshiba Semiconductor |
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97 / 224 page  TMP93CS44/S45 2004-02-10 93CS44-95 In this mode, a programmable square wave is generated by inverting timer output each time the 8-bit up counter (UC2) matches the timer registers TREG2 and TREG3. However, it is required that the set value of TREG2 is smaller than that of TREG3. Though the up counter (UC3) of timer 3 is not used in this mode, UC3 should be set for counting by setting TRUN<T3RUN> to 1. Figure 3.7.14 shows the block diagram for this mode. Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode When the double buffer of TREG2 is enabled in this mode, the value of register buffer will be shifted in TREG2 each time TREG3 matches UC2. Use of the double buffer makes easy the handling of low duty waves (when duty is varied). Figure 3.7.15 Operation of Register Buffer Q2 Q1 Match with TREG2 and up counter Match with TREG 3 Q3 Q2 (Up counter = Q1) (Up counter = Q2) Shift from register buffer TREG 2 (Register buffer) write TREG2 (Value to be compared) Register buffer Selector 8-bit up counter (UC2) Comparator Comparator φT1 φT4 φT16 T32MOD<T2CLK1:0> TFF3 TREG2 Register buffer TREG3 Selector TRDC<TR2DE> TREG2-WR TRUN<T2RUN> TO3 TFFCR <TFF3C1:0, TFF3IE> INTT2 INTT3 Shift trigger Internal data bus Inversion |
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