TMP93CS44 datasheet(78/224 Pages) TOSHIBA

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TMP93CS44/S45

2004-02-10

93CS44-76

3.6.4

Bus Width/Wait Control

An image of the actual bus width/wait control is shown below. Out of the whole memory

area, address areas that can be specified are divided into four parts. Addresses from

000000H to 3FFFFFH are divided differently: 7F00H to 7FFFH is specified for WAITC0;

880H to 7FFFH, for WAITC1; and 8000H to 3FFFFFH, for WAITC2. The reason is that a

device other than ROM (e.g., RAM or I/O) might be connected externally.

7F00H to 7FFFH (256 bytes) for WAITC0 are mapped mainly for possible expansions to

external I/O.

880H to 7FFFH (approx. 31 Kbytes) for WAITC1 are mapped there mainly for possible

extensions to external RAM.

8000H to 3FFFFFH (approx. 4 Mbytes) for WAITC2 are mapped mainly for possible

extensions to external ROM. With the TMP93CS45, which does not have a built-in ROM,

the program is externally read at address FF0000H in this setting (16-bit bus, 2 waits).

With the TMP93CS44 which has a built-in ROM, addresses from FF0000H to FFFFFFH

are used as the internal ROM area; WAITC2 is disabled in this area. After reset, the CPU

reads the program from the built-in ROM in 16-bit bus, 0 WAIT mode.

Note 1: Access priority is highest for built-in I/O, then built-in memory, and lowest for the bus

width/wait controller.

Note 2: External areas other than WAITC0 to WAITC2 are accessed in 0 WAIT mode. In the

TMP93CS45, when the AM8/ AM16 pin is set to “L”, the data bus width is fixed to 16-bit.

When the AM8/ AM16 pin is set to “H”, it is fixed to 8 bits. In the TMP93CS44, the data

bus width is always fixed to 16 bits.

When using the bus width/wait controller, do not specify the same address area more

than once. (However, when addresses 7F00H to 7FFFH for WAITC0 and 880H to

7FFFH for WAITC1 are specified, in other words, specifications overlap, only the

WAITC0 setting is active.)

000000H

7F00H

8000H

400000H

800000H

C00000H

FFFFFFH

<B0C1:0>

= 00

<B0C1:0>

= 01

<B0C1:0>

= 10

<B0C1:0>

= 11

(Mainly for I/O)

WAITC0

<B1C1:0>

= 00

<B1C1:0>

= 01

<B1C1:0>

= 10

<B1C1:0>

= 11

(Mainly for RAM)

WAITC1

880H

<B2C1:0>

= 01

<B2C1:0>

= 10

<B2C1:0>

= 11

(Mainly for ROM)

WAITC2

<B2C1:0>

= 01

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