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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP93CS44 датащи(PDF) 96 Page - Toshiba Semiconductor |
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TMP93CS44 датащи(HTML) 96 Page - Toshiba Semiconductor |
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96 / 224 page  TMP93CS44/S45 2004-02-10 93CS44-94 The comparator match signal is output from timer 2 each time the up counter UC2 matches TREG2, where the up counter UC2 is not be cleared. With the timer 3 comparator, the match detect signal is output at each comparator timing when up counter UC3 and TREG3 values match. When the match detect signal is output simultaneously from both comparators of timer 2 and timer 3, the up counters UC2 and UC3 are cleared to 0, and the interrupt INTT3 is generated. If inversion is enabled, the value of the timer flip-flop TFF3 is inverted. Example: When TREG3 = 04H and TREG2 = 80H Figure 3.7.12 Timer Output by 16-Bit Timer Mode (3) 8-bit PPG (Programmable pulse generation) output mode Square wave pulse can be generated at any frequency and duty by timer 2. The output pulse may be either low active or high active. In this mode, timer 3 cannot be used. Timer 2 outputs pulse to TO3 pin (Also used as P41). Figure 3.7.13 8-Bit PPG Output Waveforms tH TREG2 TREG3 TREG2 and UC2 match (Interrupt INTT2) TREG3 and UC2 match (Interrupt INTT3) TO3 t tL Inversion Value of up counter (UC3, UC2) Timer 2 comparator match detect signal Interrupt INTT3 0080H 0180H 0280H 0380H 0480H 0000H Timer output TO3 |
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