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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP93CS44 датащи(PDF) 27 Page - Toshiba Semiconductor |
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TMP93CS44 датащи(HTML) 27 Page - Toshiba Semiconductor |
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27 / 224 page  TMP93CS44/S45 2004-02-10 93CS44-25 Table 3.3.5 Halt Releasing Source and Halt Releasing Operation Interrupt Receiving Status Interrupt Enable (Interrupt level) ≥ (Interrupt mask) Interrupt Disable (Interrupt level) < (Interrupt mask) HALT mode RUN IDLE2 IDLE1 STOP RUN IDLE2 IDLE1 STOP NMI ♦ ♦ ♦ ♦*1 − − − − INTWDT ♦ × × × − − − − INT0 ♦ ♦ ♦ ♦*1 ○ ○ ○ ○*1 INT1, INT4 to INT7 ♦ ♦ × × × × × × INTT0 to INTT3 ♦ ♦ × × × × × × INTTR4 to INTTR7 ♦ ♦ × × × × × × INTTO4, INTTO5 ♦ ♦ × × × × × × INTRX0, INTTX0 ♦ ♦ × × × × × × INTRX1, INTTX1 ♦ ♦ × × × × × × INTS2 ♦ ♦ × × × × × × Interrupt INTAD ♦ × × × × × × × RESET ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦: After releasing the HALT mode, CPU starts interrupt processing. (RESET initializes LSI.) ○: After releasing the HALT mode, CPU starts executing an instruction that follows the HALT instruction. ×: It can not be used to release the HALT mode. −: This combination type does not exist because the priority level (Interrupt request level) of non-maskable interrupts is fixed to highest priority level “7”. *1: Releasing the HALT mode is executed after passing the warm-up time. Note: When releasing the HALT mode is executed by INT0 interrupt of the level mode in the interrupt enabled status, hold level “H” until starting interrupt processing. If level “L” is set before holding level “L”, interrupt processing is correctly started. (Example releasing “RUN” mode) INT0 interrupt releases halt state when the RUN mode is on. Address 8203H LD (IIMC), 00H ; Selects interrupt rising edge for INT0. 8206H LD (INTE0AD), 06H ; Sets interrupt level to “6” for INT0. 8209H EI 5 ; Sets interrupt level to “5” for CPU. 820BH LD (WDMOD), 00H ; Sets HALT mode to “RUN”. 820EH HALT ; Halts CPU. 820FH LD XX, XX When halt is released by reset, the states (Including those of the internal RAM) before halt state was entered can be maintained. However, if the HALT instruction is executed within the internal RAM, the contents of the RAM may not be maintained. In this case, we recommend releasing the halt state using INT0. Halt releasing source INT0 interrupt routine RETI INT0 |
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