TMP93CS44 datasheet(53/224 Pages) TOSHIBA

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TMP93CS44/S45

2004-02-10

93CS44-51

Table 3.5.2 I/O Registers and Specification (2/2)

I/O Register

Port

Name

Specification

PnCR

PnFC

Input port

Output port

P44

TO4 output

Input port/TI6/INT6 input

P45

Output port

Input port/TI7/INT7 input

P46

Output port

None

Input port

Output port

Port 4

P47

TO6 output

Input port

Port 5

P50 to P57

AN0 to AN7 input (Note 4)

None

Input port (without pull up)

Input port (with pull up)

Output port

P60

TXD0 output

Input port/RXD0 input (without pull up)

Input port/RXD0 input (with pull up)

P61

Output port

None

Input port/SCLK0/

CTS

input (without pull up)

Input port/SCLK0/

CTS

input (with pull up)

Output port

P62

SCLK0 output

Input port (without pull up)

Input port (with pull up)

Output port

P63

TXD1 output (Note 3)

Input port/RXD1 input (without pull up)

Input port/RXD1 input (with pull up)

P64

Output port

None

Input port/SCLK1/

CTS

input (without pull up)

Input port/SCLK1/

CTS

input (with pull up)

Output port

P65

SCLK1 output

Input port

Output port (Note 5)

Port 6

P66, P67

XT1/2 (Note 6)

None

Input port/ WAIT input

P70

Output port

Input port

Port 7

P71 to P77

Output port

None

X: Don’t care, n: Port number

Note 4: Using P50 to P57 pins as input channels for the AD converter, the channels are

selected by ADMOD1<ADCH2:0>.

Note 5: Using P66 and P67 pins as the output ports, output is through the open-drain buffer.

Note 6: Using P66 and P67 pins as the XT1 to XT2, oscillation is enabled by the SYSCR0

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