TMP93CS44 datasheet(74/224 Pages) TOSHIBA

74 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-72

3.6

Bus Width/Wait Controller and AM8/ AM16 Pin

TMP93CS44/S45 have a built-in controller used to control wait ( WAIT pin) and data bus size

(8 or 16 bits) for any of the three block address areas.

And AM8/ AM16 pin selects external data bus width for TMP93CS45.

3.6.1

AM8/ AM16 pin

(1) TMP93CS44

Set this pin to “H”. After reset, the CPU accesses the internal ROM with 16-bit bus

width. The bus width when the CPU accesses an external area is set by the bus

width/wait control register (Described at 3.6.3) and the registers of Port 1. (The value 1

of this pin is ignored and the value set by register is active.)

(2) TMP93CS45

1. With fixed external 16-bit data bus and external 16-bit data bus or 8-bit data bus

is selectable

Set this pin to “L”. Port1, AD8 to AD15 and A8 to A15 pins are fixed to AD8 to

AD15 functions. The values set in port 1 control register and port 1 function

The external data bus width is set by the bus width/wait control register which

is described in section 3.6.3.

It is necessary to set the program memory to be accessed to 16-bit data bus after

reset.

2. With fixed external 8-bit data bus

Set this pin to “H”. Port1, AD8 to AD15 and A8 to A15 pins are fixed to A8 to

A15 functions. The values set in port 1 control register and port 1 function register

are invalid.

The values of bit4: <B0BUS>, <B1BUS>, and <B2BUS>, in the bus width/wait

control register described in section 3.6.3 are invalid. The external 8-bit data bus

is fixed.

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