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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP93CS44 датащи(PDF) 77 Page - Toshiba Semiconductor |
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TMP93CS44 датащи(HTML) 77 Page - Toshiba Semiconductor |
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77 / 224 page  TMP93CS44/S45 2004-02-10 93CS44-75 7 6 5 4 3 2 1 0 Bit symbol B0BUS B0W1 B0W0 B0C1 B0C0 WAITC0 (0068H) Read/Write W After reset 0 0 0 0 0 Prohibit read- modify- write Function 0: 16-bit bus 1: 8-bit bus 00: 2 waits 01: 1 wait 10: (1 + N) waits 11: 0 waits 00: 7F00H to 7FFFH 01: From 400000H 10: From 800000H 11: From C00000H Bit symbol B1BUS B1W1 B1W0 B1C1 B1C0 WAITC1 (0069H) Read/Write W After reset 0 0 0 0 0 Prohibit read- modify- write Function 0: 16-bit bus 1: 8-bit bus 00: 2 waits 01: 1 wait 10: (1 + N) waits 11: 0 waits 00: 880H to 7FFFH 01: From 400000H 10: From 800000H 11: From C00000H Bit symbol B2BUS B2W1 B2W0 B2C1 B2C0 WAITC2 (006AH) Read/Write W After reset 0 0 0 0 0 Prohibit read- modify- write Function 0: 16-bit bus 1: 8-bit bus 00: 2 waits 01: 1wait 10: (1 + N) waits 11: 0 waits 00: From 8000H 01: From 400000H 10: From 800000H 11: From C00000H Figure 3.6.1 Bus Width/Wait Control Registers Table 3.6.1 Dynamic Bus Sizing CPU Data Operand Data Size Operand Start Address Memory Data Size CPU Address D15 to D8 D7 to D0 8 bits 2n + 0 xxxxx b7 to b0 2n + 0 (Even number) 16 bits 2n + 0 xxxxx b7 to b0 8 bits 2n + 1 xxxxx b7 to b0 8 bits 2n + 1 (Odd number) 16 bits 2n + 1 b7 to b0 xxxxx 2n + 0 xxxxx b7 to b0 8 bits 2n + 1 xxxxx b15 to b8 2n + 0 (Even number) 16 bits 2n + 0 b15 to b8 b7 to b0 2n + 1 xxxxx b7 to b0 8 bits 2n + 2 xxxxx b15 to b8 2n + 1 b7 to b0 xxxxx 16 bits 2n + 1 (Odd number) 16 bits 2n + 2 xxxxx b15 to b8 2n + 0 xxxxx b7 to b0 2n + 1 xxxxx b15 to b8 2n + 2 xxxxx b23 to b16 8 bits 2n + 3 xxxxx b31 to b24 2n + 0 b15 to b8 b7 to b0 2n + 0 (Even number) 16 bits 2n + 2 b31 to b24 b23 to b16 2n + 1 xxxxx b7 to b0 2n + 2 xxxxx b15 to b8 2n + 3 xxxxx b23 to b16 8 bits 2n + 4 xxxxx b31 to b24 2n + 1 b7 to b0 xxxxx 2n + 2 b23 to b16 b15 to b8 32 bits 2n + 1 (Odd number) 16 bits 2n + 4 xxxxx b31 to b24 xxxxx: During a read, data input to the bus is ignored. At write, the bus is at high impedance and the write strobe signal remains non-active. |
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