TMP93CS44 datasheet(93/224 Pages) TOSHIBA

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TMP93CS44/S45

2004-02-10

93CS44-91

Timer Register Double Buffer Control Register

Bit symbol

TR2DE

−

TRDC

(0029H)

Read/Write

R/W

After reset

Function

0: Double

buffer

disable

1: Double

buffer

enable

Always

write “0”.

Figure 3.7.9 8-Bit Timer Related Register (5/5)

(1) 8-bit timer mode

Four interval timers 0, 1, 2, 3 can be used independently as 8-bit interval timer.

1. Generating interrupts in a fixed cycle (in case of timer 1)

To generate timer 1 interrupt at constant intervals using timer 1 (INTT1), first

stop timer 1 then set the operation mode, input clock, and a cycle to T10MOD and

TREG1 register, respectively. Then, enable interrupt INTT1 and start the

counting of timer 1.

Example: To generate timer 1 interrupt every 1 second at fs

= 32 kHz, set each register in the following manner.

* Clock condition

System clock:

Low frequency (fs)

Prescaler clock: Low frequency (fs)

MSB

LSB

TRUN

← − X − − − − 0 −

Stop timer 1, and clear it to “0”.

T10MOD

← 0 0 X X 1 0 − −

Set the 8-bit timer mode, and select

φT16 (4 ms at fs = 32

kHz) as the input clock.

TREG1

← 1 1 1 1 1 0 1 0

Set the timer register 1 s

÷ φT16 = 250 = FAH

INTET10

← 1 1 0 1 − − − −

Enable INTT1, and set it to Level 5.

TRUN

← 1 X − − − − 1(

Start timer 1 counting.

X: Don’t care, (: No change

Use the Table 3.7.1 for selecting the input clock.

Note:

The input clock of timer 0 and timer 1 are different from as follows.

Timer 0: TI0 input, (T1, (T4, (T16.

Timer 1: Match output of timer 0, (T1, (T16, (T256.

Operation of timer register 2 double butter

Disable

Enable

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