TMP93CS44 datasheet(33/224 Pages) TOSHIBA

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TMP93CS44/S45

2004-02-10

93CS44-31

3.4

Interrupts

TLCS-900 interrupts are controlled by the CPU interrupt mask flip-flop <IFF2:0> and the

built-in interrupt controller.

Altogether the TMP93CS44/S45 have the following 33 interrupt sources:

Internal interrupts ............................ 26

•

Software interrupts: 8

•

Illegal instruction execution: 1

•

Interrupts from built-in I/Os: 17

External interrupts ........................... 7

•

External pins ( NMI , INT0, INT1, INT4, to INT7)

A fixed individual interrupt vector number is assigned to each interrupt source; six levels of

priority can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed

priority of 7.

When an interrupt is generated, the interrupt controller sends the value of the priority of the

interupt source to the CPU. When more than one interrupt is generated simultaneously, the

interrupt controller sends the value of the highest priority (7 for non-maskable interrupts is the

highest) to the CPU.

The CPU compares the value of the priority sent with the value in the CPU interrupt mask

interrupt is accepted. The value in the CPU interrupt mask register <IFF2:0> can be changed

using the EI instruction (Executing EI n changes the contents of <IFF2:0> to n). For example,

programming EI 3 enables acceptance of maskable interrupts with a priority of 3 or greater, and

non-maskable interrupts which are set in the interrupt controller. The DI instruction (<IFF2:0>

= 7) operates in the same way as the EI 7 instruction. Since the priority values for maskable

interrupts are 0 to 6, the DI instruction is used to disable acceptance of maskable interrupts.

The EI instruction becomes effective immediately after execution (with the TLCS-90, the EI

instruction becomes effective after execution of the subsequent instruction).

In addition to the general-purpose interrupt processing mode described above, there is also a

micro DMA processing mode. Micro DMA is a mode used by the CPU to automatically transfer

byte or word data. It enables the CPU to process interrupts such as data saves to built-in I/Os at

high speed.

Figure 3.4.1 is a flowchart showing overall interrupt processing.

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