TMP93CS44 datasheet(157/224 Pages) TOSHIBA

157 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-155

(6) Transmitter/receiver selection

Set SBICR2<TRX> to 1 for operating the TMP93CS44/S45 as a transmitter. Set

<TRX> to 0 for operation as a receiver. When data with an addressing format is

transferred in the slave mode, when a slave address with the same value that an

I2CAR or the GENERAL CALL is received (All 8-bit data are 0 after the start

condition), <TRX> is set to 1 by the hardware if the direction bit (R/W) sent from the

master device is 1, and is set to 0 by the hardware if the bit is 0. In the master mode,

after the acknowledge signal is returned from the slave device, <TRX> is set to 0 by the

hardware if a transmitted direction bit is 1, and set to 1 by the hardware if it is 0. When

the acknowledge signal is not returned, the current condition is maintained.

<TRX> is cleared to 0 by the hardware after the stop condition on the I2C bus is

detected.

The following shows <TRX> change conditions in each mode and <TRX> after

changing.

Mode

Direction Bit

Change Condition

<TRX> after

Changing

Slave Mode

A received slave address is the same as

a value set to I2CAR.

Master Mode

ACK signal is returned.

When the TMP93CS44/S45 operates in the free data format, the slave address and

the direction bit are not recognized. They are handled as data just after generating a

start condition. The TRX was not changed by the hardware.

(7) Start/stop condition generation

When SBICR2<BB> is 0, the start condition and slave address and direction bit are

output by writing 1 to SBICR2<MST, TRX, BB, PIN>. It is necessary to set 1 to

SBICR1<ACK> beforehand.

Figure 3.10.9 Start Condition Generation and Slave Address Generation

When SBICR2<BB> is 1, a sequence of generating the stop condition is started by

writing 1 to <MST, TRX, PIN> and 0 to <BB>. Do not modify the contents of <MST,

TRX, BB, PIN> until the stop condition is generated on a bus.

When a stop condition is generated and the SCL line on the bus is set to low level by

another device, a stop condition is generated after releasing the SCL line.

345678

A0R/ W

Slave address and the direction bit

Acknowledge signal

Start condition

SCL line

SDA line

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