TMP93CS44 datasheet(155/224 Pages) TOSHIBA

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TMP93CS44/S45

2004-02-10

93CS44-153

(1) Acknowledge mode specification

Set SBICR1<ACK> to “1” for operation in the acknowledge mode. The

TMP93CS44/S45 generates an additional clock pulse for an acknowledge signal when

operating in the master mode. In the transmitter mode during the clock pulse cycle, the

SDA pin is released in order to receive the acknowledge signal from the receiver. In the

receiver mode during the clock pulse cycle, the SDA pin is set to the low level in order to

generate the acknowledge signal.

Set <ACK> to 0 for operation in the non-acknowledge mode. The TMP93CS44/S45

does not generate a clock pulse for the acknowledge signal when operating in the

master mode.

In the acknowledgment mode, when the TMP93CS44/S45 is the slave mode, clocks

are counted for the acknowledge signal. During the clock for the acknowledge signal,

when a received slave address matches to a slave address set to the I2CAR or a

GENERAL CALL is received, the SDA pin is set to low level generating an

acknowledge signal.

After a received slave address matches to a slave address set to the I2CAR and a

GENERAL CALL is received, in the transmitter mode during the clock for the

acknowledge signal, the SDA pin is released in order to receive the acknowledge signal

from the receiver. In the receiver mode, the SDA pin is set to low level generating an

acknowledge signal.

In the non-acknowledgment mode, when the TMP93CS44/S45 is the slave mode,

clocks for the acknowledge signal are not counter.

(2) Number of transfer bits

SBICR1<BC2:0> are used to select a number of bits for transmitting and receiving

data.

Since <BC2:0> are cleared to 000 as a start condition, a slave address and direction

bit transmissions are executed in 8 bits. Other than these, <BC2:0> retain a specified

value.

(3) Serial clock

1. Clock source

SBICR1<SCK2:0> are used to select a maximum transfer frequency output on

the SCL pin in the master mode. Set the baud rates, which have been calculated

according to the formula below, to meet the specifications of the I2C bus, such as

the smallest pulse width of tLOW.

Figure 3.10.7 Clock Source

tHIGH

tLOW

1/fscl

tLOW = 2

n/fFPH

tHIGH = 2

n/fFPH + 12/fFPH

fscl

= 1/(tLOW + tHIGH)

fFPH

× 2n + 12

<SCK2:0>

(Bits 2 to 0 in the SBICR1)

000

001

010

011

100

101

110

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