TMP93CS44 datasheet(161/224 Pages) TOSHIBA

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TMP93CS44/S45

2004-02-10

93CS44-159

(3) 1-word data transfer

Test SBISR<MST> by the INTS2 interrupt process after a 1-word data transfer is

completed, and determine whether the mode is a master or slave.

1. When <MST> is “1” (Master mode)

Test SBISR<TRX> and determine whether the mode is a transmitter or

receiver.

When <TRX> is “1” (Transmitter mode)

Check SBISR<LRB>. When <LRB> is 1, a receiver does not request data.

Implement the process to generate the stop condition (Described later) and

terminate data transfer.

When <LRB> is 0, the receiver requests new data. When the next transmitted

data is 8 bits, write it to the SBIDBR. When the next transmitted data is other

than 8 bits, set SBICR1<BC2:0>, set SBICR1<ACK> to 1, and write the

transmitted data to the SBIDBR. After writing the data, SBISR<PIN> becomes 1,

the serial clock pulse is generated for transferring a new 1 word of data from the

SCL pin, and then the 1-word data is transmitted. After the data is transmitted,

the INTS2 interrupt request occurs. <PIN> becomes 0 and the SCL pin is set to

the low level. If the data to be transferred is more than one word in length, repeat

the procedures from <LRB> test mentioned above.

Figure 3.10.13 Example of when <BC2:0> = “000”, <ACK> = “1” (Transmitter mode)

When <TRX> is “0” (Receiver mode)

When the next transmitted data is other than 8 bits, set SBICR1<BC2:0> again.

Set <ACK> to 1 and read the received data from the SBIDBR to release the SCL

line. The read data is undefined immediately after the slave address is set. After

the data is read, <PIN> becomes 1. Serial clock pulse for transferring new 1 word

of data is defined SCL and outputs “L” level from SDA pin with acknowledge

timing.

The INTS2 interrupt request then occurs and <PIN> becomes 0. The SCL pin is

set to the low level. The TMP93CS44/S45 outputs a clock pulse for 1 word of data

transfer and the acknowledge signal each time that received data is read from the

SBIDBR.

345678

Acknowledge signal

from a receiver

Write to SBIDBR

SCL pin

SDA pin

<PIN>

INTS2

interrupt request

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