TMP93CS44 datasheet(141/224 Pages) TOSHIBA

141 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-139

12.

Signal generation timing

1) In UART mode

Receive

Mode

9-Bit

8-Bit + Parity

8-Bit, 7-Bit + Parity, 7-Bit

Timing for Interrupt

Generation

Center of last bit (Bit8)

Center of last bit

(Parity bit)

Center of stop bit

Timing for Framing

Error Generation

Center of stop bit

Timing for Parity Error

Generation

−

Center of last bit

(Parity bit)

Center of stop bit

Timing for Overrun

Error Generation

Center of last bit

(Bit8)

Center of last bit

(Parity bit)

Center of stop bit

Note:

In 9-bit and 8-bit + parity mode, interrupts coincide with the ninth bit pulse. Thus,

when serving the interrupt, it is necessary to want for a 1-bit period (to allow the

stop bit to be transferred) to allow checking for a framing error.

Send

Mode

9-Bit

8-Bit

+ Parity

8-Bit, 7-Bit

+ Parity, 7-Bit

Timing for Interrupt

Generation

Immediately before

stop bit sent

←

2) In I/O interface mode

SCLK0 output mode

Immediately after rise of last SCLK0 signal

(See Figure 3.9.17)

Timing for Send

Interrupt Generation

SCLK0 input mode

Immediately after rise (Rising mode) or fall (Falling mode) of

last SCLK0 signal

(See Figure 3.9.18)

SCLK0 output mode

Immediately after final SCLK0 (when received data are

transferred to receive buffer 2 (SC0BUF) (See Figure 3.9.19)

Timing for Receive

Interrupt Generation

SCLK0 input mode

Immediately after final SCLK0 (when received data are

transferred to receive buffer 2 (SC0BUF) (See Figure 3.9.20)

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