TMP93CS44 datasheet(140/224 Pages) TOSHIBA

140 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-138

9. Transmission buffer

Transmission buffer (SC0BUF) shifts out and sends the transmission data written

from the CPU from the least significant bit (LSB) in order. When all bits are shifted out,

the transmission buffer becomes empty and generates INTTX0 interrupt.

10. Parity control circuit

When serial channel control register SC0CR<PE>is set to 1, it is possible to transmit

and receive data with parity. However, parity can be added only in 7- or 8-bit UART

mode. With SC0CR <EVEN> register, even (odd) parity can be selected.

For transmission, parity is automatically generated according to the data written in

the transmission buffer SC0BUF, and data are transmitted after being stored in

SC0BUF<TB7> when in 7-bit UART mode while in SC0MOD<TB8> when in 8-bit

UART mode. <PE> and <EVEN> must be set before transmission data are written in

the transmission buffer.

For receiving, data are shifted in the receiving buffer 1, and parity is added after the

data are transferred in the receiving buffer 2 (SC0BUF), and then compared with

SC0BUF<RB7> when in 7-bit UART mode and with SC0MOD<RB8> when in 8-bit

UART mode. If they are not equal, a parity error occurs, and SC0CR<PERR> flag is

set.

11. Error flag

Three error flags are provided to increase the reliability of receiving data.

1. Overrun error <OERR>

If all bits of the next data are received in receiving buffer 1 while valid data are

stored in receiving buffer 2 (SC0BUF), an overrun error will occur.

2. Parity error <PERR>

The parity generated for the data shifted in receiving buffer 2 (SC0BUF) is

compared with the parity bit received from RXD pin. If they are not equal, a parity

error occurs.

3. Framing error <FERR>

The stop bit of received data is sampled three times around the center. If the

majority is 0, a framing error occurs.

TMP93CS44 датащи(PDF) 140 Page - Toshiba Semiconductor