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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP93CS44 датащи(PDF) 144 Page - Toshiba Semiconductor |
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TMP93CS44 датащи(HTML) 144 Page - Toshiba Semiconductor |
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144 / 224 page  TMP93CS44/S45 2004-02-10 93CS44-142 2. Receiving In SCLK output mode, synchronous clock is outputted from SCLK0 pin and the data are shifted in the receiving buffer 1 whenever the receive interrupt flag INTES0<IRX0C> is cleared by reading the received data. When 8-bit data are received, the data will be transferred in the receiving buffer 2 (SC0BUF) at the timing shown below, and INTES0<IRX0C> will be set again to generate INTRX0 interrupt. Figure 3.9.19 Receiving Operation in I/O Interface Mode (SCLK output mode) In SCLK input mode, the data is shifted in the receiving buffer 1 when SCLK input becomes active while the receive interrupt flag INTES0<IRX0C> is cleared by reading the received data. When 8-bit data is received, the data will be shifted in the receiving buffer 2 (SC0BUF) at the timing shown below, and INTES0<IRX0C> will be set again to generate INTRX0 interrupt. Figure 3.9.20 Receiving Operation in I/O Interface Mode (SCLK input mode) Note: For data receiving, the system must be placed in the receive enable state (SC0MOD<RXE> = 1). IRX0C Bit0 Bit2 Bit6 Bit7 Timing to shift data in the receiving buffer 2 SCLK0 RXD0 Bit1 Generate INTRX0 Bit0 Bit1 Bit6 Bit7 Bit2 Generate INTRX0 Timing to shift data in the receiving buffer 2 RXD0 SCLK0 input (SCLKS = 0: Rising edge mode) SCLK0 input (SCLKS = 1: Falling edge mode) |
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