TMP93CS44 datasheet(138/224 Pages) TOSHIBA

138 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-136

6. Receiving buffer

To prevent overrun error, the receiving buffer has a double buffer structure.

Received data are stored one bit by one bit in the receiving buffer 1 (Shift register

type). When 7 bits or 8 bits of data is stored in the receiving buffer 1, the stored data

are transferred to the receiving buffer 2 (SC0BUF), generating an interrupt INTRX0.

The CPU reads only receiving buffer 2 (SC0BUF). Even before the CPU reads the

receiving buffer 2 (SC0BUF), the received data can be stored in the receiving buffer 1.

However, unless the receiving buffer 2 (SC0BUF) is read before all bits of the next data

are received by the receiving buffer 1, an overrun error occurs. If an overrun error

occurs, the contents of the receiving buffer 1 will be lost, although the contents of the

receiving buffer 2 and SC0CR<RB8> is still preserved.

The parity bit added in 8-bit UART mode and the most significant bit (MSB) in 9-bit

UART mode are stored in SC0CR<RB8>.

When in 9-bit UART mode, the wakeup function of the slave controllers is enabled by

setting SC0MOD<WU> to 1, and interrupt INTRX0 occurs only when SC0CR<RB8> is

set to 1.

7. Transmission counter

Transmission counter is a 4-bit binary counter which is used in UART mode and,

counts by SIOCLK clock, generating TXDCLK every 16 clock pulses.

Figure 3.9.12 Generation of Transmission Clock

8. Transmission controller

•

I/O interface mode

In SCLK0 output mode with the setting of SC0CR<IOC>

= 0, the data in the

transmission buffer are output bit by bit to TXD0 pin at the rising edge of shift

clock which is output from SCLK0 pin.

In SCLK0 input mode with the setting of SC0CR<IOC>

= “1”, the data in the

transmission buffer are output bit by bit to TXD0 pin at the rising edge or falling

edge of SCLK0 input according to the setting of SC0CR<SCLKS> register.

•

UART mode

When transmission data are written in the transmission buffer sent from the

CPU, transmission starts at the rising edge of the next TXDCLK, generating a

transmission shift clock TXDSFT.

SIOCLK

TXDCLK

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