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TMP93CS41 датащи(PDF) 164 Page - Toshiba Semiconductor

номер детали TMP93CS41
подробное описание детали  CMOS 16-Bit Microcontroller
PDF  248 Pages
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производитель  TOSHIBA [Toshiba Semiconductor]
домашняя страница  http://www.semicon.toshiba.co.jp/eng
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TMP93CS41 датащи(HTML) 164 Page - Toshiba Semiconductor

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TMP93CS40/TMP93CS41
2004-02-10
93CS40-162
Figure 3.10.10 Output Waveforms for 4-phase 2-step Excitation (Normal rotation)
The output from PG0 (P6) is latched on the rising edge of the trigger signal from the
timer.
The direction of shift is specified by the setting of PG01CR<CCW0>: Normal rotation
(PG00
→PG01→PG02→PG03) is selected when <CCW0> is set to “0”; reverse rotation
(PG00
←PG01←PG02←PG03) is selected when <CCW0> is set to “1”. 4-phase 1-step
excitation will be selected when only one bit is set to “1” during the initialization of PG,
while 4-phase 2-step excitation will be selected when two consecutive bits are set to “1”.
The value in the shift alternate registers are ignored when 4-phase 1-step/2-step
excitation mode is selected.
Figure 3.10.11 shows the block diagram.
Figure 3.10.11 Block Diagram for 4-phase 1-step Excitation/2-step Excitation (Normal rotation)
b4
Trigger signal
from timer
PG00 (P60)
PG01 (P61)
PG02 (P62)
PG03 (P63)
b7
b5
b6
b7
b4
b5
b6
b6
b7
b4
b5
b5
b6
b7
b4
b4
b5
b6
b7
Initial value of PG0REG
= 1100××××
PG03
PG03 (P63)
PG01
PG02
SA03
SA02
SA01
SA00
PG0 output latch
Shift alternate register
Indicates that shifting takes place on
the rising edge of the trigger signal
from the timer.
PG00
b7
b3
b6
b2
b5
b1
b4
b0
PG02 (P62)
PG01 (P61)
PG00 (P60)



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