TMP93CS41 datasheet(94/248 Pages) TOSHIBA

94 / 248 page

TMP93CS40/TMP93CS41

20004-02-10

93CS40-92

3.6.4

Chip Select Addresses Image

An image of the actual addresses which can be specified by chip select is shown below.

Out of the whole memory area, address areas that can be specified are divided into four

parts. Addresses from 000000H to 3FFFFFH are further divided as follows: 7F00H to

7FFFH is specified for CS0; 880H to 7FFFH, for CS1; and 8000H to 3FFFFFH, for CS2.

The reason is that a device other than ROM (e.g., RAM or I/O) might be connected

externally.

7F00 to 7FFFH (256 bytes) designated as CS0 are mapped mainly for possible

expansions to external I/O.

880H to 7FFFH (approx. 31 Kbytes) designated as CS1 are mapped mainly for possible

extensions to external RAM.

8000H to 3FFFFFH (approx. 4 Mbytes) designated as CS2 are mapped mainly for

possible extensions to external ROM. After resetting, CS2 is enabled in a 16-bit bus and

2-wait configuration. In the case of the TMP93CS41, which does not have a built-in ROM,

the program is externally read at address 8000H with these settings (16-bit bus, 2 waits).

With the TMP93CS40, which does have a built-in ROM, addresses from 8000H to 17FFFH

are used as the internal ROM area; CS2 is disabled in this area. After resetting, the CPU

reads the program from the built-in ROM in 16-bit bus, 0-wait mode.

Note 1:

Access priority is highest for built-in I/O, then built-in memory, and lowest for the chip

select/wait controller.

Note 2:

External areas other than CS0 to CS2 are accessed in 0 wait mode.

For the TMP93CS40, the data bus width is fixed at 16 bits. For the TMP93CS41, the

data bus width is 16 bits when AM8/ AM16 = 0, and 8 bits when AM8/ AM16 = 1.

When using the chip select/wait controller, do not specify the same address area

more than once. (However, when specifications overlap, only one of them will be

utilized. For example, when addresses 7F00H to 7FFFH for CS0 are specified at the

same time as 880H to 7FFFH for CS1, only the CS0 setting and pin will be active.)

Note 3:

When the bus is released ( BUSAK = “0”), the CS0 to CS2 pins are also released

(the output buffer is OFF). For further information about the state of pins, refer to the

note about the bus release in section 3.5 “Functions of Ports”.

000000H

7F00H

8000H

400000H

800000H

C00000H

FFFFFFH

CS0

B0C1, 0

= “01”

B0C1, 0

= “10”

B0C1, 0

= “11”

(Mainly for I/O)

B0C1, 0

= “00”

CS1

B1C1, 0

= “01”

B1C1, 0

= “10”

B1C1, 0

= “11”

(Mainly for RAM)

B1C1, 0

= “00”

CS2

B2C1, 0

= “01”

B2C1, 0

= “10”

B2C1, 0

= “11”

(Mainly for ROM)

B2C1, 0

= “00”

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