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TMP93CS41 датащи(PDF) 168 Page - Toshiba Semiconductor |
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TMP93CS41 датащи(HTML) 168 Page - Toshiba Semiconductor |
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168 / 248 page ![]() TMP93CS40/TMP93CS41 2004-02-10 93CS40-166 When using a trigger signal from timer 4, set either T4FFCR<EQ5T4> or T4MOD<EQ5T5> to “1”; a trigger is generated when the value in UC4 and the value in TREG5 match. When using a trigger signal from timer 5, set T5FFCR<EQ7T6> to “1”; a trigger is generated when the value in UC5 and the value in TREG7 match. (4) Application of PG and timer output As explained in the previous section trigger signal from timer, the timings for shifting PG and inverting TFF differ depending on the timer mode. An application which operates PG while operating an 8-bit timer in PPG mode is explained below. To drive a stepping motor, a synchronizing signal is required for the excitation timing, in addition to the value of each phase (PG output). In this application, port 6 is used as a stepping motor control port to output a synchronizing signal to the TO1 pin (shared with P71). Figure 3.10.14 Output Waveforms for 4-Phase 1-step Excitation Setting example: 7 6 5 4 3 2 1 0 TRUN ← − X − − − − 0 0 Stop timer 0, and clear it to zero. TMOD ← 1 0 X X X X 0 1 Set timer 0 and timer 1 to PPG output mode and select φT1 as the input clock. TFFCR ← X X X 0 0 1 1 X Enable TFF1 inversion and set TFF1 to “1”. TREG0 ← * * * * * * * * Set the duty of TO1 to TREG0. TREG1 ← * * * * * * * * Set the cycle of TO1 to TREG1. P7CR ← X X X X − − 1 − P7FC ← X X X X − − 1X Assign P71 as TO1. P6CR ← − − − − 11 1 1 P6FC ← − − − − 11 1 1 Assign P60 to P63 as PG0. PG01CR ← − − − − 0 0 0 1 Set PG0 to 4-phase 1-step excitation mode. PG0REG ← * * * * * * * * Set an initial value. TRUN ← 1 X − − − − 1 1 Start timer 0 and timer 1. X: Don’t care, −: No change TO1 (P71) TREG1 PG00 (P60) TREG0 PG01 (P61) PG02 (P62) PG03 (P63) |
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