TMP93CS41 datasheet(167/248 Pages) TOSHIBA

167 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-165

Setting example: To drive channel 0 (PG0) using 4-phase 1-2 step excitation (Normal

rotation) when timer 0 is selected, set each register as follows.

TRUN

← − X − − − − − 0

Stop timer 0, and clear it to zero.

TMOD

← 0 0 X X − − 01

Set 8-bit timer mode and select

φT1 as the input clock for

timer 0.

TFFCR

← X X X 0 1 0 1 0

Clear TFF1 to zero and enable the inversion trigger using

timer 0.

TREG0

← *

Set the cycle in the timer register.

P6CR

← − − − − 1 1 1 1

Set bits P60 to P63 to output mode.

P6FC

← − − − − 1 1 1 1

Set bits P60 to P63 to PG output.

PG01CR

← − − − − 0 0 1 1

Select PG0 4-phase 1 to 2 step excitation mode and

normal rotation.

PG0REG

← 1 1 0 0 1 0 0 0

Set an initial value.

TRUN

← 1 X − − − − − 1

Start timer 0.

X: Don’t care,

−: No change

(3) Trigger signal from timer

The trigger signal from the timer used by PG is not the same as the trigger signal for the

timer flip-flop (TFF1, TFF4, TFF5, and TFF6); they differ as shown in Table 3.10.1

depending on the operation mode of the timer.

Table 3.10.1 Trigger Signal Selection

TFF1 Inversion

PG Shift

8-bit timer mode

Selected by TFFCR<TFF1IS> when the

up counter value matches TREG0 or

TREG1 value

Selected by TFFCR<TFF1IS> when the

up counter value matches TREG0 or

TREG1 value

16-bit timer mode