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TMP93CS41 датащи(PDF) 64 Page - Toshiba Semiconductor |
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TMP93CS41 датащи(HTML) 64 Page - Toshiba Semiconductor |
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64 / 248 page ![]() TMP93CS40/TMP93CS41 2004-02-10 93CS40-62 Port 2 Register 7 6 5 4 3 2 1 0 P2 Bit symbol P27 P26 P25 P24 P23 P22 P21 P20 (0006H) Read/Write R/W After reset Input mode (Output latch register is cleared to “0”.) Port 2 Control Register 7 6 5 4 3 2 1 0 P2CR Bit symbol P27C P26C P25C P24C P23C P22C P21C P20C (0008H) Read/Write W After reset 0 0 0 0 0 0 0 0 Function <<See table below.>> Port 2 Function Register 7 6 5 4 3 2 1 0 P2FC Bit symbol P27F P26F P25F P24F P23F P22F P21F P20F (0009H) Read/Write W After reset 0 0 0 0 0 0 0 0 Function <<See table below.>> Figure 3.5.6 Registers for Port 2 P2FC<P2XF> P2CR <P2XC> 0 1 0 Input port Address data bus (A7 to A0) 1 Output port Address bus (A23 to A16) Port 2 function setting Note 1: Read-modify-write is prohibited for registers P2CR and P2FC. Note 2: When port P2 is used in the input mode, P2 register controls the built-in pull-down resistor. Read-modify-write is prohibited in the input mode or the I/O mode, as it may affect the states of the pull-up/pull-down resistors. Note 3: <P2XF> is bit X in register P2FC; <P2XC> is bit X in register P2CR. To set as an address bus A23 to A16, set P2FC after setting P2CR. |
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