TMP93CS41 datasheet(16/248 Pages) TOSHIBA

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TMP93CS40/TMP93CS41

2004-02-10

93CS40-14

3.3

Dual Clock, Standby Function

Dual clock, standby control circuits are comprised of a system clock controller, prescaler clock

controller, internal clock pin output function and standby controller.

The oscillator operating modes are classified as either (a) Single clock mode (using only the

X1 and X2 pins), or (b) Dual clock mode (using the X1, X2, XT1, and XT2 pins).

Figure 3.3.1 shows state diagrams for the two clock modes. Figure 3.3.2 shows the

corresponding block diagram, Figure 3.3.3 displays functions of the I/O registers and Table

3.3.1 lists correspondences between alternative states of the system clock and those of the CPU,

oscillator and internal I/O components.

(a) Single Clock Mode State Diagram

(b) Dual Clock Mode State Diagram

Figure 3.3.1 State Diagrams

The clock frequency input from the X1 and X2 pins is called fc, and the clock frequency input

from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1<SYSCK> and

<GEAR2:0> is called the system clock fFPH. The divided clock of fFPH is defined as the system

clock fSYS, and one cycle of fSYS is defined as one state.

RUN mode

(Stops only CPU)

IDLE2 mode

(Stops CPU and AD)

IDLE1 mode

(Operates only oscillator)

STOP mode

(Stops all circuits)

RESET

NORMAL mode

(fc/gear value/2)

Instruction

Interrupt

Instruction

Interrupt

Instruction

Interrupt

Instruction

Interrupt

Release reset

RUN mode

(Stops only CPU)

IDLE2 mode

(Stops CPU and AD)

IDLE 1 mode

(Operates only oscillator)

STOP mode

(Stops all circuits)

RESET

NORMAL mode

(fc/gear value/2)

Instruction

Interrupt

Instruction

Interrupt

Instruction

Interrupt

Release reset

RUN mode

(Stops only CPU)

IDLE 2 mode

(Stops CPU and AD)

IDLE 1 mode

(Operates only oscillator)

SLOW mode

(fs/2)

Instruction

Interrupt

Instruction

Interrupt

Instruction

Interrupt

Instruction

Interrupt

Instruction

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