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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP93CS41 датащи(PDF) 26 Page - Toshiba Semiconductor |
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TMP93CS41 датащи(HTML) 26 Page - Toshiba Semiconductor |
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26 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-24 (2) CLK pin The CLK pin outputs the internal clock signal fSYS divided by 2. The type of output is determined by one bit in the clock output control register, CKOCR<CLKEN>. Writing 1 sets the clock output, and writing “0” sets the CLK pin to high impedance. CKOCR<CLKEN> is set to “0” upon resetting. During resetting, the CLK pin is internally pulled up regardless of the value of the <CLKEN> register. Table 3.3.4 States of the <CLKEN> Register, and CLK Pin Operation after Reset Type No. CKOCR<CLKEN> CLK Pin Operation TMP93CS40 0 High impedance TMP93CS41 1 fSYS/2 clock output Note: To set CKOCR<CLKEN> = “0” and set the CLK pin to high impedance, an external pull-up resistor is needed to prevent current from flowing to the input buffer of the CLK pin. |
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