TMP93CS41 datasheet(47/248 Pages) TOSHIBA

47 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-45

(3) Transfer mode register details

Mode

Transfer destination address INC mode .................................... for I/O to memory

(DMADn

+)←(DMASn)

DMACn

←DMACn − 1

if DMACn

= 0 then INT.

16 states

(1.6

µs)

Transfer destination address DEC mode ................................... for I/O to memory

(DMADn

−)←(DMASn)

DMACn

←DMACn − 1

if DMACn

= 0 then INT.

16 states

(1.6

µs)

Transfer source address INC mode........................................... for memory to I/O

(DMADn)

←(DMASn+)

DMACn

←DMACn − 1

if DMACn

= 0 then INT.

16 states

(1.6

µs)

Transfer source address DEC mode ......................................... for memory to I/O

(DMADn)

←(DMASn−)

DMACn

←DMACn − 1

if DMACn

= 0 then INT.

16 states

(1.6

µs)

Fixed address mode.................................................................. I/O to I/O

(DMADn)

←(DMASn)

DMACn

←DMACn − 1

if DMACn

= 0 then INT.

16 states

(1.6

µs)

Read-only mode ........................................................................ for DRAM refresh

Dummy

←(DMASn)

; Reads 4 bytes.

DMASn

←DMASn + 4 ; Increments lower word only.

DMACn

←DMACn − 1

14 states

(1.4

µs)

Counter mode ........................................................................... for interrupt counter

DMASn

←DMASn + 1

DMACn

←DMACn − 1

if DMACn

= 0 then INT.

11 states

(1.1

µs)

Note 1: n: corresponds to micro DMA channels 0 to 3.

DMADn

+/DMASn+: Post-increment (Increments register value after transfer.)

DMADn

−/DMASn−: Post-decrement (Decrements register value after transfer.)

Note 2: Execution time: When setting source address/destination address area to 16-bit bus, 0 waits. Clock

condition: fc

= 20 MHz, clock gear: 1 (fc)

Note 3: Do not use any codes for transfer mode registers other than those indicated above.

Note: When setting values for this

Z: 0

= byte transfer, 1 = word transfer

Execution time

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