TMP93CS41 datasheet(38/248 Pages) TOSHIBA

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TMP93CS40/TMP93CS41

2004-02-10

93CS40-36

3.4.1

General-purpose Interrupt Processing

When accepting an interrupt, the CPU operates as follows. In the cases of software

interrupts or interrupts generated by the CPU because of attempts to execute illegal

instructions, the following steps (1) and (3) are not executed.

(1) The CPU reads the interrupt vector from the interrupt controller. When more than one

interrupt with the same priority level is generated simultaneously, the interrupt

controller generates interrupt vectors in accordance with the default priority, then

clears the interrupt request. The default priority is fixed as follows: The smaller the

vector value, the higher the priority.

(2) The CPU pushes the program counter and the status register to the system stack area

(Area indicated by the system mode stack pointer (XSP)).

(3) The CPU sets a value in the CPU interrupt mask register <IFF2:0> that is higher by 1

than the priority level value of the accepted interrupt. However, if the accepted

interrupt’s priority value is 7, 7 is set without an increment.

(4) The CPU increments the interrupt nesting counter (INTNEST).

(5) The CPU jumps to an address stored in the 8000H

+ interrupt vector, then starts the

interrupt processing routine.

The following table shows the number of processing states corresponding to steps 1

to 5 above.

Number of Interrupt Processing States

Bus Width of

Stack Area

Bus Width of Interrupt

Vector Area

Max Mode

Min Mode

8 bits

16 bits

8 bits

16 bits

The RETI instruction is usually used to complete the interrupt processing.

Executing this instruction restores the contents of the program counter and the status

registers, and decrements the interrupt nesting counter (INTNEST).

Though acceptance of non-maskable interrupts cannot be disabled by programming,

acceptance of maskable interrupts can. A priority can be set for each source of

maskable interrupts. The CPU accepts any interrupt request with a priority higher

than the current value in the CPU mask register <IFF2:0>. The CPU mask register

<IFF2:0> is then set to a value higher by 1 than the priority of the accepted interrupt.

Thus, if another interrupt is generated with a priority level higher than the interrupt

currently being processed, the CPU accepts the interrupt with the higher level, causing

interrupt processing to nest.

If an interrupt request with a priority higher than the currently-processed interrupt

is generated during the time that CPU is processing the above steps (1) to (5), and is

accepted before the first instruction in the interrupt processing routine is executed,

this will cause interrupt processing to nest. (The nesting process is the same as in the

case of overlapping each non-maskable interrupt (Level 7).) The CPU does not accept

an interrupt request of the same priority level as that of the interrupt currently being

processed.

Resetting initializes the CPU mask registers <IFF2:0> to the value 7; therefore,

acceptance of all maskable interrupts is disabled.

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