TMP93CS41 datasheet(36/248 Pages) TOSHIBA

36 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-34

3.4

Interrupts

Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and the built-in

interrupt controller.

Altogether the TMP93CS40 and TMP93CS41 have the following 29 interrupt sources:

•

Interrupts from the CPU, 9 sources

(Software interrupts, and illegal (Undefined) instruction execution)

•

Interrupts from external pins ( NMI , INT0, and INT4 to INT7), 6 sources

•

Interrupts from built-in I/Os, 14 sources

A fixed individual interrupt vector number is assigned to each interrupt source; any one of six

levels of priority can also be assigned to each maskable interrupt. Non-maskable interrupts

have a fixed priority of 7.

When an interrupt is generated, the interrupt controller sends the value of the priority of the

interrupt source to the CPU. When more than one interrupt is generated simultaneously, the

interrupt controller sends the value of the highest priority (7 for non-maskable interrupts is the

highest) to the CPU.

The CPU compares the value of the priority sent, with the value in the CPU interrupt mask

interrupt is accepted. However, software interrupts and illegal instruction execution interrupts

are not compared with the <IFF2:0> register. They are given top priority. The value in the CPU

interrupt mask register <IFF2:0> can be changed using the EI instruction. Executing EI n

changes the contents of <IFF2:0> to n. For example, programming EI 3 enables acceptance of

maskable interrupts with a priority of 3 or greater, and non-maskable interrupts which are set

in the interrupt controller. When EI or EI 0 is programmed, maskable interrupts with a priority

of 1 or greater, and non-maskable interrupts are enabled in the interrupt instructions (In the

same way as the EI 1).

The DI instruction operates in the same way as the EI 7 instruction, setting <IFF2:0>

= 7.

Since the priority values for maskable interrupts are 0 to 6, the DI instruction is used to disable

acceptance of maskable interrupts. The EI instruction becomes effective immediately after

execution. (With the TLCS-90, the EI instruction becomes effective after execution of the next

following instruction.)

In addition to the general-purpose interrupt processing mode described above, there is also a

micro DMA processing mode. Micro DMA is a mode used by the CPU to automatically transfer

byte or word data. It enables the CPU to process interrupts such as data saves to built-in I/Os at

high speed.

Figure 3.4.1 is a flowchart showing overall interrupt processing.

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