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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP93CS41 датащи(PDF) 166 Page - Toshiba Semiconductor |
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TMP93CS41 датащи(HTML) 166 Page - Toshiba Semiconductor |
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166 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-164 The initialization sequence for 4-phase 1-2 step excitation is as follows. By rearranging the initial value b7 b6 b5 b4 b3 b2 b1 b0 to b7 b3 b6 b2 b5 b1 b4 b0, three consecutive bits are set to 1 and the other bits are set to 0 (Positive logic). For example, if b7, b3, and b6 are set to 1, the initial value becomes 11001000, producing the output waveforms shown in Figure 3.10.12. To generate a negative logic output waveform, the 1’s and 0’s in the initial value must be inverted. For example, to change the output waveform shown in Figure 3.10.12 negative logic, change the initial value to 00110111. The operation will be explained below for channel 0. The output from PG0 (P6) and from the shift alternate register (SA0) for pattern generation is latched on the rising edge of the trigger signal from the timer. The shift direction is set by PG01CR<CCW0>. Figure 3.10.13 shows the block diagram. Figure 3.10.13 Block Diagram for 4-phase 1- to 2-step Excitation (Normal rotation) PG03 PG03 (P63) PG01 PG02 SA03 SA02 SA01 SA00 PG0 output latch Shift alternate register Indicates that shifting takes place on the rising edge of the trigger signal from the timer. PG00 b7 b3 b6 b2 b5 b1 b4 b0 PG02 (P62) PG01 (P61) PG00 (P60) |
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