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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AMC131M01DFMR датащи(PDF) 24 Page - Texas Instruments |
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AMC131M01DFMR датащи(HTML) 24 Page - Texas Instruments |
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24 / 81 page  bandwidth results in lower noise, whereas higher bandwidth results in higher noise. See Table 7-1 for the noise specifications for various OSR settings. The device must be in standby mode when changing the OSR. Setting the OSR[2:0] bits to a new value while the ADC is generating conversion data can result in unexpected behavior of the ADC output. Table 8-4. OSR Settings and Data Rates for Nominal Main Clock Frequencies POWER MODE NOMINAL MAIN CLOCK FREQUENCY fMOD(1) OSR OUTPUT DATA RATE High-resolution (HR) 8.192 MHz 4.096 MHz 64 64 kSPS 128 32 kSPS 256 16 kSPS 512 8 kSPS 1024 4 kSPS 2048 2 kSPS 4096 1 kSPS 8192 500 SPS 16384 250 SPS Low-power (LP) 4.096 MHz 2.048 MHz 64 32 kSPS 128 16 kSPS 256 8 kSPS 512 4 kSPS 1024 2 kSPS 2048 1 kSPS 4096 500 SPS 8192 250 SPS 16384 125 SPS (1) Programmable clock divider is set to NDIV = 2. 8.3.11.1 Digital Filter Implementation Figure 8-6 shows the digital filter implementation of the AMC131M01. The modulator bitstream feeds two parallel filter paths: a sinc3 filter and a fast-settling filter path. Modulator Bitstream Sinc 3 Regular Filter Fast-Settling Filter Sinc 1 Averager (OSR > 1024) Global Chop Logic PHASEx[9:0] PGA_GAINx[2:0] OSR 1024 Power-up or Reset MUX MUX 1 0 1 0 Calibration Logic, Gain scaling OSR = 1024 OSR[2:0] OSR[2:0] Phase Delay Figure 8-6. Digital Filter Implementation 8.3.11.1.1 Fast-Settling Filter At power-up or after a device reset, the AMC131M01 selects the fast-settling filter to allow for settled output data generation with minimal latency. The fast-settling filter has the characteristic of a first-order sinc filter (sinc1). AMC131M01 SBASA57 – SEPTEMBER 2023 www.ti.com 24 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AMC131M01 |
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