AMC131M01DFMR datasheet(65/81 Pages) TI

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and CHn_GCAL_LSB registers according to the method described in the Calibration Registers section. The host

can program the measured inverted gain values into these registers to have them automatically corrected for

each sample.

9.1.6 Troubleshooting

Table 9-1 lists common issues faced when designing with the AMC131M01 and the corresponding solutions.

This list is not comprehensive.

Table 9-1. Troubleshooting Common Issues Using the AMC131M01

ISSUE

POSSIBLE ROOT CAUSE

POSSIBLE SOLUTION

The DRDY pin is toggling at half the expected

frequency.

The DRDY_FMT bit is set to 1b and ADC

conversion data are not being read. The

updates of the conversion data in the FIFO

buffer drive the DRDY pin. If the host does

not read the conversion data, the data in

the FIFO buffer are updated every other

conversion. This update causes the DRDY

pin to toggle at half the output data rate.

See the ADC Output Buffer and FIFO Buffer

section for a detailed explanation.

Read data after each DRDY falling edge

following the recommendations given in the

Collecting Data for the First Time or After a

Pause in Data Collection section.

The F_RESYNC bit is set in the STATUS

word even though this bit was already

cleared.

The SYNC/RESET pin is being toggled

asynchronously to CLKIN.

The SYNC/RESET pin functions as a

constant synchronization check, rather than

a convert start pin. See the Synchronization

section for more details on the intended

usage of the SYNC/RESET pin.

The same ADC conversion data are output

multiple times before changing.

The ADC does not recognize the data as

being read because not all ADC channel data

are read by the host.

Read all data words in the output data

frame, including those for channels that are

disabled.

The SEC_FAIL bit in the STATUS register is

set, even if the power on the secondary side

appears to be stable, for example after an

SPI write operation.

Writing data to any of the ADC configuration

registers on the high side also sets the

SEC_FAIL bit until the transmission over the

isolation barrier is complete.

Read the SEC_FAIL bit in the STATUS

0b, before reading ADC conversion data.

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AMC131M01

SBASA57 – SEPTEMBER 2023

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