AMC131M01DFMR datasheet(30/81 Pages) TI

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8.4.1.3 RESET Command

The AMC131M01 can be reset with the SPI RESET command (0011h).

The device communicates in frames of a fixed length. See the SPI Communication Frames section for details

regarding SPI data framing on the AMC131M01. The RESET command is transmitted in the first word of the

data frame on DIN, but the command is not latched and executed by the device until the entire frame is

complete. Terminating the frame early causes the RESET command to be ignored. Five words are required to

complete a frame on the AMC131M01.

A reset occurs immediately after the command is latched. The host must wait for tREGACQ before communicating

with the device to make sure the registers have assumed the default settings. Follow the procedure described in

the Start-Up Behavior After a Pin Reset or RESET Command section after the device is reset.

8.4.2 Start-Up Behavior After Power-Up

The AMC131M01 does not generate conversion data automatically after power-up because the integrated

DC/DC converter is disabled initially. For the ADC to operate, the DC/DC converter must be enabled after

power-up, and a stable supply voltage at the HLDO_OUT pin must be established that serves as the power

supply for the circuitry on the secondary (high) side.

A recommended procedure for powering up the AMC131M01 is described in this section. Figure 8-13 depicts a

timing diagram for the device behavior when this recommended sequence is used. Figure 8-14 provides a flow

diagram that displays the recommended sequence in a graphical form.

Follow these steps to ensure a correct start-up behavior at power-up:

• Power up the DVDD supply.

• The transition of DRDY from low to high indicates a valid supply voltage on the primary side is established,

and also indicates the SPI interface is ready for communication.

• Configure the clock divider by setting the CLK_DIV[1:0] bits in the CLOCK register as needed.

• Configure the modulator clock frequency by setting the DCDC_FREQ[3:0] bits in the DCDC_CTRL register;

see the Clocking and Power Modes section for details.

• Enable the DC/DC converter by setting the DCDC_EN bit in the DCDC_CTRL register to 1b.

• Configure all other registers of the AMC131M01 before the external clock is applied to the CLKIN pin.

• Provide the main clock at the CLKIN input to start operation of the integrated DC/DC converter, and to make

sure that the secondary power supply at the HLDO_OUT pin is generated.

• The transition of the SEC_FAIL bit in the STATUS register from high to low indicates that the secondary

power supply at the HLDO_OUT pin is established and the ADC conversion data output is valid. Confirm

device operation by reading the SEC_FAIL bit, and verify that this bit is set to 0b, before reading any

conversion data from the ADC. There are two options for reading the SEC_FAIL bit in the STATUS register:

sending a NULL command results in a response including the STATUS word, or sending a register read

command to read the STATUS register. The SEC_FAIL bit is a latched bit; therefore, at least two read

commands are required to confirm that this bit transitioned from high to low; the first read command clears

the logic high value that is latched during device power-up. Use the second read command to verify that the

SEC_FAIL bit is set to 0b, indicating that the secondary supply is valid. If the SEC_FAIL bit still reads 1b as a

result of the second read command, continue reading the SEC_FAIL bit until this bit reads 0b before reading

any conversion data from the ADC.

AMC131M01

SBASA57 – SEPTEMBER 2023

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