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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AMC131M01DFMR датащи(PDF) 50 Page - Texas Instruments |
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AMC131M01DFMR датащи(HTML) 50 Page - Texas Instruments |
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50 / 81 page  8.6.2 STATUS Register (Address = 01h) [Reset = 0540h] Return to the Summary Table. Figure 8-29. STATUS Register 15 14 13 12 11 10 9 8 LOCK F_RESYNC REG_MAP CRC_ERR CRC_TYPE RESET WLENGTH[1:0] R-0b R-0b R-0b R-0b R-0b R-1b R-01b 7 6 5 4 3 2 1 0 FUSE_FAIL SEC_FAIL RESERVED DRDY0 R-0b R-1b R-00000b R-0b Table 8-14. STATUS Register Field Descriptions Bit Field Type Reset Description 15 LOCK R 0b SPI interface lock indicator Indicates the SPI interface is locked by the lock command. The bit is reset to 0b by the unlock command. 0b = Unlocked 1b = Locked 14 F_RESYNC R 0b ADC resynchronization indicator This bit is set each time the ADC resynchronizes. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register. 0b = No resynchronization occurred 1b = Resynchronization occurred 13 REG_MAP R 0b Register map CRC fault indicator Indicates a register map CRC fault occurred. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register. 0b = No register map CRC fault occurred 1b = Register map CRC fault occurred 12 CRC_ERR R 0b SPI input CRC error indicator Indicates a SPI input CRC fault occurred. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register. 0b = No CRC error 1b = Input CRC error occurred 11 CRC_TYPE R 0b CRC type indicator Indicates the CRC type. This bit is cleared by a device reset. 0b = 16-bit CCITT 1b = 16-bit ANSI 10 RESET R 1b Reset status indicator The device reset indicator is triggered by the RESET pin, power-on-reset or the RESET command. This bit is cleared by writing 0b to the RESET bit in the MODE register. 0b = Not reset 1b = Reset occurred 9:8 WLENGTH[1:0] R 01b Data word length indicator Indicates the data word frame length. This bit is cleared by a device reset. 00b = 16 bit 01b = 24 bits 10b = 32 bits; zero padding 11b = 32 bits; MSB sign extension 7 FUSE_FAIL R 0b Fuse parity fault indicator Indicates a fault of the internal memory. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register. If the physical fault persists, the indicator is set again automatically. 0b = Fuse parity OK 1b = Fuse parity not OK 6 SEC_FAIL R 1b High-side supply fault indicator Indicates a fault of the high-side output of the DC/DC converter, or a communication error during the data transmission across the isolation barrier. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register. 0b = High-side supply OK 1b = High-side supply not OK 5:1 RESERVED R 00000b Reserved Always reads 00000b 0 DRDY0 R 0b Channel 0 ADC data available indicator 0b = No new data available 1b = New data are available AMC131M01 SBASA57 – SEPTEMBER 2023 www.ti.com 50 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AMC131M01 |
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