AMC131M01DFMR datasheet(22/81 Pages) TI

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8.3.9 Clocking and Power Modes

An LVCMOS clock must be provided at the CLKIN pin continuously when the AMC131M01 is running in normal

operation. The frequency of the clock can be scaled in conjunction with the power mode to provide a tradeoff

between power consumption and dynamic range.

The PWR[1:0] bits in the CLOCK register allow the device to be configured in one of two power modes:

high-resolution (HR) or low-power (LP) mode. Changing the PWR[1:0] bits scales the internal bias currents

to achieve the expected power levels. The external clock frequency must follow the guidance provided in the

Recommended Operating Conditions table corresponding to the intended power mode for the device to perform

according to the specification.

The main clock must be externally provided at the CLKIN pin. As shown in Figure 8-5, a user-programmable

clock divider divides the main clock to derive the internal modulator clock (MOD_CLK). By default, the main

clock provided at the CLKIN pin is divided by NDIV = 2 to generate a 50% duty cycle internal modulator clock. As

listed in Table 8-2, the divider ratio NDIV can be changed to values of 4, 8, and 12 using the CLK_DIV[1:0] bits in

the CLOCK register.

÷ by NDIV

(2, 4, 8 or 12)

CLKIN

CLK_DIV[1:0]

MOD_CLK

fCLKIN

fMOD

ADC

Figure 8-5. Programmable Clock Divider Block Diagram

Table 8-2. Modulator Clock Divider Selection

CLK_DIV[1:0]

NDIV FOR MOD_CLK

00b

01b

10b

11b

The clock frequency range of the internal DC/DC converter must be synchronized with the modulator clock

to minimize interference. To optimize the DC/DC converter internal clock, the actual frequency value of the

modulator clock must be written to the DCDC_CTRL register immediately after device power-up. The modulator

clock frequency is a result of the frequency provided at the CLKIN pin and the selected divider ratio (for example,

if a 4-MHz clock frequency is provided at the CLKIN pin, and the divider ratio is set to 4, then the frequency of

the modulator clock MOD_CLK is 1 MHz). The correct modulator clock frequency value must be configured in

the DCDC_CTRL register, as given in Table 8-3, by writing to the DCDC_FREQ[3:0] register bits immediately

after start-up.

An example calculation is:

• Main clock: fCLKIN = 8.192 MHz

• Divider ratio: NDIV= 4

• Resulting modulator clock: fCLKIN / NDIV = 2.048 MHz

• Modulator clock frequency is within the range: 1.926 MHz to 2.051 MHz; see Table 8-3

• Required DCDC_FREQ[3:0] bit setting: 1000b; see Table 8-3

AMC131M01

SBASA57 – SEPTEMBER 2023

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