AMC131M01DFMR datasheet(38/81 Pages) TI

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In the case of a write register (WREG) command where multiple registers are written, the frame extends to

accommodate the additional data. See the WREG section for more details on the WREG command.

See the Commands section for a list of all valid commands and the corresponding responses on the

AMC131M01.

Under special circumstances, a data frame can be shortened by the host. See the Short SPI Frames section for

more information about artificially shortening communication frames.

8.5.1.8 SPI Communication Words

An SPI communication frame with the AMC131M01 is made of words. Words on DIN can contain commands,

responses, register settings during a register read, ADC conversion data, or the CRC of the output data.

Words can be 16, 24, or 32 bits. The word size is configured by the WLENGTH[1:0] bits in the MODE register.

The device defaults to a 24-bit word size. Commands, responses, CRC, and registers always contain 16 bits of

actual data. These words are always most significant bit (MSB) aligned, and therefore the least significant bits

(LSBs) are zero-padded to accommodate 24- or 32-bit word sizes. ADC conversion data are nominally 24 bits.

The ADC truncates the eight LSBs when the device is configured for 16-bit word size. There are two options

for 32-bit communication available for ADC data that are configured by the WLENGTH[1:0] bits in the MODE

8.5.1.9 Short SPI Frames

The SPI frame can be shortened to only send commands and receive responses if the ADCs are disabled and

no ADC data are being output by the device. Read out all expected output data words from each sample period

if the ADCs are enabled. Reading all data output with each frame ensures predictable DRDY pin behavior. If

reading out all data on each output data period is not feasible, see the Collecting Data for the First Time or After

a Pause in Data Collection section on how to begin reading data again after a pause from when the ADCs were

last enabled.

A short frame is not possible when using the RESET command. A full frame must be provided for a device reset

to take place when providing the RESET command.

8.5.1.10 Communication Cyclic Redundancy Check (CRC)

The AMC131M01 features a cyclic redundancy check (CRC) engine on both input and output data to mitigate

SPI communication errors. The CRC word is 16 bits wide for either input or output CRC. Coverage includes all

words in the SPI frame where the CRC is enabled, including zero-padded or sign-extended bits.

CRC on the SPI input is optional and can be enabled and disabled by writing the RX_CRC_EN bit in the

MODE register. Input CRC is disabled by default. The device checks the provided input CRC against the CRC

generated based on the input data. A CRC error occurs if the CRC words do not match. The device does not

execute any commands, except for the WREG command, if the input CRC check fails. A WREG command

always executes even when the CRC check fails. The device sets the CRC_ERR bit in the STATUS register for

all cases of a CRC error. The response on the output in the SPI frame following the frame where the CRC error

occurred is that of a NULL command, which means the STATUS register plus the conversion data are output in

the following SPI frame. The CRC_ERR bit is cleared when the STATUS register is output.

Output CRC is not optional and always appears at the end of the output frame. The host can ignore the data if

output CRC is not used.

There are two types of CRC polynomials available: CCITT CRC and ANSI CRC (CRC-16). The CRC setting

determines the algorithm for both the input and output CRC. The CRC type is programmed by the CRC_TYPE

bit in the MODE register. Table 8-7 lists the details of the two CRC types.

The CRC calculation is initialized with the seed value of FFFFh to detect errors in the event that DIN or DOUT

are stuck low.

AMC131M01

SBASA57 – SEPTEMBER 2023

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