AMC131M01DFMR datasheet(20/81 Pages) TI

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reverse breakdown voltage. Take care to prevent input voltages or currents from exceeding the limits provided in

the Absolute Maximum Ratings table.

8.3.5 Input Multiplexer

The AMC131M01 has a dedicated input multiplexer. The multiplexer controls which signals are routed to the

ADC. Configure the input multiplexer using the MUX0[1:0] bits in the CH0_CFG register. The input multiplexer

allows the following inputs to be connected to the ADC:

• The analog input pins

• HGND, which is used for offset calibration

• Positive DC test signal

• Negative DC test signal

See the Internal Test Signals section for more information about the test signals. Figure 8-4 shows a diagram of

the input multiplexer on the AMC131M01.

AIN0P

HGND

AIN0N

DC Test

Signal

–

To Positive

PGA Input

To Negative

PGA Input

MUX0[1:0] = 00

MUX0[1:0] = 01

MUX0[1:0] = 10

MUX0[1:0] = 11

Figure 8-4. Input Multiplexer

8.3.6 Programmable Gain Amplifier (PGA)

The AMC131M01 features an integrated programmable gain amplifier (PGA) that provides gains of 1, 2, 4, 8, 16,

32, 64, and 128. The gain is controlled by the PGAGAIN0[2:0] bits in the GAIN register.

Changing the PGA gain scales the differential full-scale input voltage range (FSR) of the ADC. Equation 3

describes the relationship between FSR and gain. Equation 3 uses the internal reference voltage, 1.2 V, as the

scaling factor without accounting for gain error caused by tolerance in the reference voltage.

FSR = ±1.2 V / Gain

(3)

Table 8-1 shows the corresponding full-scale ranges for each gain setting.

Table 8-1. Full-Scale Range

GAIN SETTING

FSR

±1.2 V

±600 mV

±300 mV

±150 mV

±75 mV

±37.5 mV

±18.75 mV

128

±9.375 mV

The input impedance of the PGA dominates the input impedance characteristics of the AMC131M01. The

PGA input impedance for gain settings up to 4 behaves according to Equation 4 without accounting for

AMC131M01

SBASA57 – SEPTEMBER 2023

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