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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AMC131M01DFMR датащи(PDF) 73 Page - Texas Instruments |
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AMC131M01DFMR датащи(HTML) 73 Page - Texas Instruments |
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73 / 81 page  9.4.2 Layout Example Figure 9-9 shows an example layout of the AMC131M01 requiring a minimum of two PCB layers. In general, analog and digital signals for the primary (low) side are partitioned to the right and analog and digital signals for the secondary (high) side are on the left. 3: HLDO_IN 5: HGND 7: NC 8: NC 9: AIN0P +3.3 V TI Device +3.3 V Via to corresponding voltage plane or pour Via Differential RC-filter for input channel. Terminate long digital input lines with resistors to prevent reflection. Channel 0 20: DIN 19: CS 18: SCLK 17: CLKIN 16: DRDY 14: DCDC_CAP Clearance area, to be kept free of any conductive material. 4: HLDO_OUT 2: DCDC_HGND 1: DCDC_OUT 10: AIN0N Place bypass capacitor directly across ADC inputs. GPO 6: GPO 15: DGND Place DCDC_CAP and power supply decoupling capacitors close to pins. Place smaller decoupling caps closest to the device. Place smaller decoupling caps closest to the device. 13: DVDD 12: DOUT 11: SYNC/RST Top Metal Inner or Bottom Layer Metal C1 Keep layout of shunt connections symmetrical. Use separate trace for HGND connection to shunt terminal. C6 C11 C13 C10 C24 F2 F1 R8 R9 C9 C17 C15 C16 GND GND ISO_GND ISO_GND Place ferrites Close to the device to improve EMI performance. Figure 9-9. Layout Example www.ti.com AMC131M01 SBASA57 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: AMC131M01 |
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