AMC131M01DFMR datasheet(27/81 Pages) TI

27 / 81 page

The offset calibration registers are used to correct for system offset error, otherwise known as zero error.

Offset error corresponds to the ADC output when the input to the system is zero. The AMC131M01 corrects

for offset errors by subtracting the contents of the OCAL0[23:0] register bits in the CH0_OCAL_MSB and

CH0_OCAL_LSB registers from the conversion result before being output. The contents of the OCAL0[23:0] bits

are interpreted by the device as 24-bit, two's-complement values.

The gain calibration registers are used to correct for system gain error. Gain error corresponds to the deviation

of gain of the system from the ideal value. The AMC131M01 corrects for gain errors by multiplying the ADC

conversion result by the value given by the contents of the GCAL0[23:0] register bits in the CH0_GCAL_MSB

and CH0_GCAL_LSB registers before being output. The contents of the GCAL0[23:0] bits are interpreted by the

device as 24-bit unsigned values corresponding to linear steps ranging from gains of 0 to 2 – (1 / 223). Table 8-6

describes the relationship between the GCALn[23:0] bit values and the gain calibration factor.

Table 8-6. GCAL0[23:0] Bit Mapping

GCAL0[23:0] VALUE

GAIN CALIBRATION FACTOR

000000h

000001h

1.19 × 10–7

800000h

FFFFFEh

2 – 2.38 × 10–7

FFFFFFh

2 – 1.19 × 10–7

The calibration registers do not need to be enabled because these registers are always in use. The OCAL0[23:0]

bits have a default value of 000000h resulting in no offset correction. Similarly, the GCAL0[23:0] bits default to

800000h resulting in a gain calibration factor of 1.

Figure 8-11 shows a block diagram illustrating the mechanics of the calibration registers of the AMC131M01.

Digital

Filter

To Interface

OCAL0[23:0]

GCAL0[23:0]

Modulator

Figure 8-11. Calibration Block Diagram

8.3.13 Register Map CRC

The AMC131M01 performs a CRC on the device register map as a means to check for unintended changes

to the registers. Enable the register map CRC by setting the REG_CRC_EN bit in the MODE register. When

enabled, the device constantly calculates the register map CRC using each bit in the writable register space.

The register addresses covered by the register map CRC on the AMC131M01 are 02h through 31h. The CRC is

calculated beginning with the MSB of register 02h and ending with the LSB of register 31h using the polynomial

selected in the CRC_TYPE bit in the MODE register.

The calculated CRC is a 16-bit value and is stored in the REGMAP_CRC register. The REG_MAP bit in the

STATUS register is set to flag the host if the register map CRC changes, including changes resulting from

response to the NULL command.

The CRC calculation is initialized with the seed value of FFFFh.

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AMC131M01

SBASA57 – SEPTEMBER 2023

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