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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AMC131M01DFMR датащи(PDF) 40 Page - Texas Instruments |
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AMC131M01DFMR датащи(HTML) 40 Page - Texas Instruments |
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40 / 81 page  8.5.2 ADC Conversion Data The device provides conversion data at the data rate set by the OSR bit in the CLOCK register. The conversion status is available as the DRDY0 bit in the STATUS register. The STATUS register content is automatically output as the response to the NULL command. Conversion data are 24 bits. The data LSBs are truncated when the device operates with a 16-bit word size. The LSBs are zero padded or the MSBs sign extended when operating with a 32-bit word size depending on the setting of the WLENGTH[1:0] bits in the MODE register. Data are given in binary two's-complement format. Use Equation 10 to calculate the size of one code (LSB). 1 LSB = (2.4 V / Gain) / 224 = +FSR / 223 (10) A positive full-scale input VIN ≥ +FSR – 1 LSB = 1.2 V / Gain – 1 LSB produces an output code of 7FFFFFh, and a negative full-scale input (VIN ≤ –FSR = –1.2 V / Gain) produces an output code of 800000h. The output clips at these codes for signals that exceed full-scale. Table 8-8 summarizes the ideal output codes for different input signals. Table 8-8. Ideal Output Code versus Input Signal INPUT SIGNAL, VIN = VAINP – VAINN IDEAL OUTPUT CODE ≥ FSR (223 – 1) / 223 7FFFFFh FSR / 223 000001h 0 000000h –FSR / 223 FFFFFFh ≤ –FSR 800000h Figure 8-20 shows the mapping of the analog input signal to the output codes. 7FFFFFh - FS ¼ 0 ¼ FS Input Voltage V IN 7FFFFEh 000001h 000000h 800000h FFFFFFh 800001h - FS 2 - 1 23 2 23 FS 2 - 1 23 2 23 Figure 8-20. Code Transition Diagram AMC131M01 SBASA57 – SEPTEMBER 2023 www.ti.com 40 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AMC131M01 |
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