AMC131M01DFMR datasheet(35/81 Pages) TI

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Figure 8-17 shows a block diagram of the global-chop mode implementation. The combined PGA and ADC

internal offset voltage is modeled as VOFS. Only this device-inherent offset voltage is reduced by global-chop

mode. Offset in the external circuitry connected to the analog inputs is not affected by global-chop mode.

VOFS

PGA

ADC

Digital

Filter

Global-Chop

Mode Control

Conversion Output

Chop Switch

AINnP

AINnN

GC_EN

+ -

Figure 8-17. Global-Chop Mode Implementation

The conversion period in global-chop mode differs from the conversion time when global-chop mode is disabled

(tDATA = OSR × tMOD). Figure 8-18 shows the conversion timing for the ADC using global-chop mode.

Sampling

Data not

settled

Swap inputs,

digital filter reset

Conversion

start

tGC_FIRST CONVERSION

Data not

settled

Global-chop delay

Modulator sampling

ADC overhead

Sampling

n + 1

Sampling

n + 1

Sampling

n + 1

Sampling

n + 2

Sampling

n + 2

Sampling

n + 2

Sampling

n + 3

Sampling

n + 3

Sampling

n + 3

Data not

settled

Data not

settled

st global-chop

conversion result

nd global-chop

conversion result

tGC_CONVERSION

tDATA

Figure 8-18. Conversion Timing With Global-Chop Mode Enabled

Every time the device swaps the input polarity, the digital filter is reset. The ADC then always takes three internal

conversions to produce one settled global-chop conversion result.

The AMC131M01 provides a programmable delay (tGC_DLY) between the end of the previous conversion period

and the beginning of the subsequent conversion period after the input polarity is swapped. This delay allows

external input circuitry to settle because the chopping switches interface directly with the analog inputs. The

GC_DLY[3:0] bits in the GLOBAL_CHOP_CFG register configure the delay after chopping the inputs. The

global-chop delay is selected in terms of modulator clock periods from 2 to 65,536 × tMOD.

The effective conversion period in global-chop mode follows Equation 8. A DRDY falling edge is generated each

time a new global-chop conversion becomes available to the host.

The conversion process in global-chop mode is restarted in the following two conditions

• Falling edge of the SYNC/RESET pin

• Change of the OSR setting

The conversion period of the first conversion after the ADC is reset is considerably longer than the conversion

period of all subsequent conversions mentioned in Equation 8 because the device must first perform two fully

settled internal conversions with the input polarity swapped. The conversion period for the first conversion in

global-chop mode follows Equation 9.

tGC_CONVERSION = tGC_DLY + 3 × OSR × tMOD

(8)

tGC_FIRST_CONVERSION = tGC_DLY + 3 × OSR × tMOD + tGC_DLY + 3 × OSR × tMOD + 44 × tMOD

(9)

Using global-chop mode reduces the ADC noise listed in Table 7-1 at a given OSR by a factor of √2 because two

consecutive internal conversions are averaged to yield one global-chop conversion result. The DC test signal

cannot be measured in global-chop mode.

8.4.7 Power Modes

In both continuous-conversion and global-chop mode, there are two selectable power modes that allow scaling

of power with bandwidth and performance: high-resolution (HR) mode and low-power (LP) mode. The mode

is selected by the PWR[1:0] bits in the CLOCK register. Changing the PWR[1:0] bits scales the internal

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