AMC131M01DFMR datasheet(23/81 Pages) TI

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Table 8-3. Modulator Clock Frequency Range

Selection for DC/DC Synchronization

MODULATOR CLOCK

FREQUENCY (MHz)

DCDC_FREQ[3:0] BIT SETTING

3.768 MHz to 4.100 MHz

0000b

3.366 MHz to 3.768 MHz

0001b

3.041 MHz to 3.366 MHz

0010b

2.773 MHz to 3.041 MHz

0011b

2.549 MHz to 2.773 MHz

0100b

2.358 MHz to 2.549 MHz

0101b

2.194 MHz to 2.358 MHz

0110b

2.051 MHz to 2.194 MHz

0111b

1.926 MHz to 2.051 MHz

1000b

1.815 MHz to 1.926 MHz

1001b

1.716 MHz to 1.815 MHz

1010b

1.627 MHz to 1.716 MHz

1011b

1.547 MHz to 1.627 MHz

1100b

1.475 MHz to 1.547 MHz

1101b

1.409 MHz to 1.475 MHz

1110b

1.400 MHz to 1.409 MHz

1111b

8.3.10 ΔΣ Modulator

The AMC131M01 uses a delta-sigma (ΔΣ) modulator to convert the analog input voltage to a one's density

modulated digital bitstream. The ΔΣ modulator oversamples the input voltage at a frequency many times greater

than the output data rate. The modulator frequency, fMOD, of the AMC131M01 is derived from the main clock

frequency (provided at the CLKIN pin) with the user-programmable clock divider; see the Clocking and Power

Modes section.

The output of the modulator is fed back to the modulator input through a digital-to-analog converter (DAC) as a

means of error correction. This feedback mechanism shapes the modulator quantization noise in the frequency

domain to make the noise more dense at higher frequencies and less dense in the band of interest. The digital

decimation filter following the ΔΣ modulator significantly attenuates the out-of-band modulator quantization

noise, allowing the device to provide excellent dynamic range.

8.3.11 Digital Filter

The ΔΣ modulator bitstream feeds into a digital filter. The digital filter is a linear-phase, finite impulse response

(FIR), low-pass, sinc-type filter that attenuates the out-of-band quantization noise of the ΔΣ modulator. The

digital filter demodulates the output of the ΔΣ modulator by averaging. The data passing through the filter are

decimated and downsampled to reduce the rate at which data come out of the modulator (fMOD) to the output

data rate (fDATA). The decimation factor is defined as per Equation 5 and is called the oversampling ratio (OSR).

OSR = fMOD / fDATA

(5)

The OSR is configurable and set by the OSR[2:0] bits in the CLOCK register. By setting the OSR[2:0] bits,

the OSR can be configured in values ranging from 128 to 16384 in binary steps. In addition, the OSR can be

configured to a value of 64 by setting the TURBO bit in the CLOCK register (turbo mode). Therefore in total,

there are nine OSR settings in the AMC131M01, allowing nine different data rate settings for any given main

clock frequency. Table 8-4 lists the OSR settings and the corresponding output data rates for the nominal CLKIN

frequencies mentioned, assuming the programmable clock divider is set to NDIV = 2.

The OSR determines the amount of averaging of the modulator output in the digital filter and, therefore, also

the filter bandwidth. The filter bandwidth directly affects the noise performance of the ADC because lower

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AMC131M01

SBASA57 – SEPTEMBER 2023

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